Specifications

. .
DOUBLE OPERAND-INSTRUCTIONS .......................... i.. ............... 17
Arithmetic Operations .................. 1. ....................................... 18
Boolean 20
BRANCHES
Instructions .............................................................
.......................................................................... .:. ..... 21
Unconditional Branch ..........................................................
I Simple Conditional Branches
..............................................
;:
Signed Conditional Branches .............................................. 23
Unsigned Conditional Branches ..........................................
JUMP ....................................................................................
9:
SUBROUTINES ............................................................................. 27
Examples
............................................................................ 28
SINGLE OPERAND INSTRUCTIONS
............................................
Multiple Precision Operations ..............................................
zi
Rotates
................................................................................ 33
Shifts
..................................................................................
34
Examples ............................................................................
36
BYTE OPERATIONS ...................................................................... 36
Double Operand Byte Instructions ......................................
36
Example .......... . ................................................................... 37
Single Operand Instructions ................................................
38
CONDITION CODE OPERATORS ................................................
MISCELLANEOUS CONTROL INSTRUCTIONS .............................. ,
i!
PROCESSOR TRAPS .................................................................... 41
Trap Instructions ............................ . ...................................
41
Stack Overflow Trap ............................................................
Bus Error Traps .................................................................. ii
Trace Traps ..........................................................................
43
CHAPTER 5 I ADDRESS ALLOCATION
ADDRESS MAP ............................................................................ 45
Interrupt and Trap Vector .................................................... 46
Processor Stack and General Storage ..................................
Peripheral Registers ............................................................
z
CORE MEMORY ............................................................................ 46
Read-Write Core Memory .................................. , ................. 46
Read-Only Core Memory ......................................................
Wordlet Memory ..................................................................
g
CHAPTER 6 PROGRAMMING OF PERIPHERALS
- DEViCE REGISTERS
......................................................
. .... . .........
CONTROL & STATUS REGISTERS ...............................................
;;
Device Function Bits ....................................... :.. ................
Memory Extension .......................................................
. ......
$
Done Enable and Interrupt Enable ......................................
Condition Bits
.............................................................
..i .... ii
Unit Bits ..............................................................................
Error Bits .............. I ..:. .........................................................
g
DATA BUFFER REGISTERS
..................................................
.: ...... 48
PROGRAMMING EXAMPLES--NON INTERRUPT ........................ 48
INTERRUPT STRUCTURE
............................................................
50
PROGRAMMING EXAMPLE ..........................................................
51
CHAPTER 7 PERIPHERAL BULLETINS
.
TELETYPE (MODEL LT33-DC/DD) ..............................................
Size
......................................................................................
;;
Power Requirement ............................................................ 53
IV