Specifications

address. A “boundary error” condition will result when the processor at-
tempts to fetch an instruction from an odd address.
Deferred index mode JMP instructions permit transfer of control to the
address contained in a selectable element of a. table of dispatch vectors.
SUBROUTINES-The subroutine call in the PDP-II provides for automatic
nesting of subroutines, regntrancy, and multiple entry points. Subroutines
may call other subroutines (or indeed themselves) to any level of nesting
without making special provision for storage of return addresses at each
level of subroutine call. The subroutine calling mechanism modifies no fixed
location in memory and thus also provides for reentrancy. This allows one
copy of a subroutine to be shared among several interrupting processes.
01 0
I I I I,
4
-Q
dsi
I I, I I,,
15 9 6 6 3 0
Operation: dst + (tmp) (tmp.is an internal processor register)
Oes) &
(push reg contents onto processor stack)
(W -+ (rea)
(PC holds location following JSR; this address
_ (tmp) + Up
now put in reg)
Condition Codes: not affected
Description: Execution time for JSR is the sum of instruction and destination
times. In execution of the JSR, the old’contents of the specified-register,
(the “linkage pointer”), are automatically pushed onto the ‘processor stack
and new linkage information placed in the register. Thus subroutines nested
within subroutines to any depth may all be called with the same linkage
re&ter. There is no need either to plan the maximum depth at which any
particular subroutine will be called or to include instructions in each routine
to save and restore the linkage pointer. Further, since all linkages are saved
in a reentrant manner-on the processor stack-execution of a subroutine
may be interrupted, the same subroutine reentered and executed by an
interrupt service routine. Execution of the initial subroutine can then be
resumed when other requests are satisfied. This process (called nesting) can
proceed to any level.
A subroutine called with a JSR reg, dst instruction can access the arugments
following the call with either autoincrement addressing, (reg) +, (if argu-
ments are accessed sequentially) or by indexed addressing, X(reg), (if ac-
cessed in random order). These addressing modes may also be deferred,
@(reg)+ and @X(reg) if the parameters are operand addresses rather than
the operands themselves.
JSR PC, dst is a special case of the PDP-11 subroutine call suitable for
subroutine calls that transmit parameters through the general registers. No
register except the program counter is modified by this call.
Another special case of the JSR instruction is JSR PC, (SP)+ which ex-
changes the top element of the processor stack and the contents of the
program counter. Use of this instruction allows two routines to swap pro-
- gram control and resume operation when recalled where they left off. Such
-routines are called “co-routines.”
Return from a subroutine is done by the RTS instruction: RTS reg loads the
&tents of the reg into the PC and pops the top element of the processor
stack into the specified register.
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