Specifications

Operation: lot + (PC) if N = 0.
Description: Tests the state of the N-bit and causes a branch if N is,clear.
BPL is the complementary operation to BMI.
Branch on Carry Set
BCS lot 1.5~s ,Z.~ALS
1 , 0, ,
31 I4 I I I I I I I
t5
8 7
0
Operation: lot + (PC) if C = 1
Description: Tests the state of the C-bit and causes a branch if C is set. It
is used to test for a carry in the result of a previous operation.
Bmnch on Carry Clear
BCC IOC
t.5 U.S. 2.61~5
1
, 0
I I
3
I I
0
I
Offset
I
I I III I I
15
8
7
0
Operation: lot + (PC) if C’= 0
Description: Tests the state of the C-bit and causes a branch if C is clear.
BCC is the complementary operation to BCS.
Branch on overflow set
BVS IOC
1.5us,2.6us
1 , 0 I 2 I I
I 4 I
offset
I I I t I 1 I
15 8 7
0
Operation: lot + (PC) if V = 1
Description: Tests the state of the V-bit (overflow) and causes a branch. if
the V-bit is set. BVS is used to detect arithmetic overflow in the previous
operation.
eranch on Overflow clear WC IOC
1.5us.2.61~~
1 I 0
I 121 PI I I I I I I 1 I
oftset
15 8 7
0
*
Operation: lot + (PC) if V = 0
Description: Tests the state of the V-bit and causes a branch if the V-bit is
clear. BVC is the complementary operation to BVS.
Signed Condiiional Branches--Particular combinations of the condition code
bits are tested with the signed conditioned branches. These instructions are
used to test the results of instructions in which the operands were consid-
ered as signed (two’s complement) values.
Note that the sense of signed comparisons differs from that of unsigned
comparisons in that in signed 16-bit, two’s complement arithmetic the
sequence of values is as follows:
23