Specifications

Bll Test BIT rrc,dst
.2.9***
* 0, 3 WC
I I I I I I
dd ,
I I 1 I
. 15 12 11 6 5 0
Operation: (src) A (dst)
Condition Codes:
Z: set if result = 0; cleared otherwise
N: set if high-order bit of result set; cleared otherwise
C: not affected
V: cleared
Description: Performs logical “and” comparison of the source and destination
operands and modifies condition codes accordingly. Neither the source nor
destination operands are affected.
The BIT instruction may be used to test whether any of the corresponding
bits that are set in the destination are also set in the source or whether
all corresponding bits set in the destination are clear in the source.
Note.that the operations of BIS, BIC, and BIT are parallel in that the same
mask may be used to set, clear and test the state of particular bits in a word.
BRANCHES-Branches have the instruction format
Opwotion exx IOC Instruction Time
operation code
offs*1
I II I I I I II 1 I,1 1 II’1 I
ts - 6 7 0
The offset is treated as a signed two’s complement displacement to be mul-
tiplied by 2 and applied to the program counter. The program counter points
to the next word in sequence. The effect is to cause the next instruction to
be taken from an address, “lot”, located up to 127. words back (-254
bytes) or 128 wordsahead (+ 256 bytes) of the branch instruction. PAL-11
gives an error indication in the instruction if “lot” is outside this range.
.
The PDP-11 assembler handles address arithmetic for the user and com-
putes and assembles the proper offsets field for branch instructions in the
form
Bxx lot
where lot is the address to which the branch is to be made. The branch
instructions have no effect on condition codes.
Unconditional Branch-
BRbnch Wncondilionol)
BR IOC
2.6~s
01 lOI I I Ol I4
I I I I I I
15
6 7
0
Operation: lot + (PC)
Description: Provides a way of transferring program control within a limited
range with a one word instruction. The execution time is equal to the in-
struction time (2.6~s) for the operation.
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