Specifications
CHAPTER 4
INSTRUCTION SET
This chapter Presents the order code for the PDP-11. Each
PDP-11
instruc-
tion is described in terms of five parameters: operation, effect on condition
codes, base timing, assembler mnemonics, and octal representation.
Special
comments are included where appropriate.
NOTATION
The following notations will be used in this section:
(XXX)
: The contents of XXX
src : The Source Address
dst
: The Destination Address
A
: Boolean “AND” Function
V : Boolean “OR” Function
tf : Boolean “Exclusive OR” Function
: Boolean ‘NOT” Function (Complement)
i
: “becomes”
: “is popped from the stack”
: “is pushed onto the stack”
INSTRUCTION TIMING
The PDP-11 is an asynchronous processor in which, in many cases, memory
and processor operations are overlapped. The execution time for an instruc-
tion is the sum of a basic instruction time and the time to determine and
fetch the source and/or destination operands. The following table shows the
addressing times required for the various modes of addressing source and
destination operands. The instruction time for each operation is given
(throughout this chapter) for the 11/20 configuration. All times stated are
subject to +20% variation.
ADDRESSING FORM
(src or dst)
R
(RI or @R
L”c’Rf
@(W +
G?-(R)
BASE(R)
@BASE(R) or @(R)
TIMING
src bs)t
0
dst Wt
0
1.5
1.4*
1.5
1.4’
1.4*
::7”
2.6*
2:;
2.6*
2.6*
3.9
3.8’
l dst time is .4 ws. less than listed time if instruction was a
CoMPare. CoMPare Byte
Bit Test, Bit Test Byte
TeST, or TeST Byte
none of which ever modify the destination word.
t referencing bytes at odd addresses adds 0.6~s to sn and dst
times.
DOUBLE OPERAND INSTRUCTIONS-Double Operand Instructions are repre-
sented in assembly language as:
OPR src, dst
,’ where src and dst are the addresses of the source and destination operands
respectively. The execution time for these operations is comprised of the
source time, the destination time; and the instruction time. The source and
destination times depend on addressing modes and are described in the pre.
ceding table.
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