Specifications

tion word may be taken as the address of an operand by specifying deferral
in immediate mode addressing. That is, instructions of the form
refer to the operand at, address A. PAL-11 assembles address cxprwssions of
this form into an address field
followed by a word containing the o
P
erand address.
MUTmE ADDRESSIF&-Relative addressing specifies the operand address
relative to the instruction location. This is accomplished by using the pc as
an index regkter. The PC is considered as a base address. The of&&, the
distance betwe’en the. location of the operand and the PC, is held in the
index word of the instruction. PAL-11 assembles instructions of the form
OPR A
(where A has not been assigned as a name of a general register) as an
instruction word with the address field
followed by an index word of the form
k-f OF TM* IIIID.2
DEFERRED RELATIVE ADDRESSING-Deferral of relative addressing permits
access to data through memory locations holding operand addresses. The
“@I” character specifies deferred addressing: i.e., OPR @A. The address field
for deferred relative addressing is
USE OF THE SP AS A GENERAL REGISTER
The processor stack pointer will in most cases be the general register used
in PDP-11 stack operations. Note that the content of SP, (SP), refers to the
top element of the stack, that -(SP) will push data onto the stack, that
(SP)+ will pop data off the stack, and that X(SP) will permit random access
of items on the stack. Since the SP is used by the processor for interrupt
handling, it has a special attribute: autoincrements and autodecrements are
always done in steps of two. Byte operations using the SP in this way will
simply leave odd addresses unmodified.
DOUBLE OPFRAND ADDRESSING
Operations which imply two operands such as add, subtract .and compare
are presented in the PDP11 by instructions which specify two addresses. The
*
instruction word for 6uch operations is of the form
Instruction Word-Double Operand Instructions
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