Specifications

NPR Requeata-NPR data transfers can be made between any two peripheral
devices without the supervision of the processor. Normally, NPR transfers
are between a mass storage device, such as a disk, and core memory.
The structure of the bus also permits device-to-device trat’ISfer% allowing.
customer-designed peripheral controllers to access other devices such as
disks directly. -
An NPR device has very fast access to the bus and can transfer at high data
rates once it has control. The processor state is not affected by the transfer:
therefore the processor can relinquish control while an instruction is in
Progress. This can occur at the end of any bus cycle except in between a
read-modify-write-sequence. (See Chapter 8 for details). In the PDP-11, an
NPR device can gain bus control in 3.5 microseconds or less. An NPR device
in COritrOl of the bus may transfer ldbit words from memory at memory
speed or every 1.2 microseconds in the PDP-ll/EO or every 1.0 microseconds
in the PDP-ll/lO.
IIIterrUpt Requests-Devices that request interrupts on the bus request lines
(BR7, BR6, BR5, BR4) can take advantage of the power and flexibility of
the processor. The entire instruction set is available for manipulating data
and status registers. When a device servicing program must be run, the task
currently under way in the central processor is interrupted and the device
service routine is initiated. Once the device request has been satisfied, the
processor returns to the interrupted task.
In the PDP-11, the return address for the interrupted routine and the proces-
sor status word are held in a “stack.” A stack is a dvnamic seauential
list of data with special provision for access from one end. A stack-is also
called a “push down” or “LIFO” (Last-In First-Out) list. Storaee and re-
trieval from stacks is called “pushing” and “popping” respecti&ly. These
operations are illustrated in Figure 2-1.
In the PDP-11, a stack is automatically maintained by the hardware for inter-
rupt processing. Thus, higher level requests can interrupt the processing of
lower level interrupt service, and automatically return control to the lower
level interrupt service routines when the higher level servicing is completed.
Here is an example of this procedure. A peripheral requires service and
requests use of the bus at one of the.BR levels (BR7, BR6, BR5, BR4). The
operations undertaken to “service” the device are as follows:
I
l.AN EMPTY
STACK
E2
El
El
E0
4. ANOTHER
PUSH
El
El
E0
5 POP
E0
,
3.PlJStlING ANOTHER
~tiW&CNTO THE
E3
I3
E4
EO
6. PUSH
E3
Fig 2-1 Illustration of Push and Pop Operations
8