Specifications

Read-only core memory (ROM) is available in 1,024 16 bit-word segments.
The access time of the ROM is 500 nanoseconds. Memory is also available in
128 16-bit word segments with a 2.0 microsecond cycle time. Both 1,024
words of read-only memory and 128 words of read-write memory mount in
a single System Unit and are a standard part of the PDP-ll/lO system.
PERIPHERAL DEVICES-The ASR-33 Teletype with low-speed paper tape
reader and punch is provided in the basic PDP-11/20 system. Options for the
.PDP-11 include a paper tape reader capable of reading 300 characters per
second, a paper tape punch with an output capacity of 50 characters per
second, and additional Teletype units. Provision is made for the addition
of numerous peripheral devices. These include standard DEC peripherals as
well as other devices which will be unique to the PDP-11.
SYSTEM INTERACTION
At any point in time only one device can be in control of the bus, or be bus
master. The master communicates with another device on the bus which is
called the slave. Usually, the established master will communicate with the
slave in the form of data transfers.
Full 16-bit words or 8-bit bytes of information can be transferred on the bus
between the master and the slave. The information can be instructions, ad-
dresses, or data. This type of ‘operation occurs when the processor, as
master, is fetching instructions, operands, and data from memory, and re-
storing the results into memory after execution of instructions. Pure data
transfers occur between a disk control and memory.
TRANSFER OF BUS MASTER-When a device (other than the central pro-
cessor) is capable of becoming bus master and requests use of the bus, it is
generally for one of two purposes: 1) to make a non-processor transfer of
data directly to or from memory, or 2) to interrupt program execution and
force the processor to branch to a specific address where an interrupt
service routine is located.
PRIORITY STRUCTURE-When a device capable of becoming. bus master
requests use of the bus, the handling of that request depends on the loca-
tion of that device in the priority structure. These factors must be considered
to determine the priority of the request;
1. The processor’s priority can be set under program control to one of
eight levels using bits 7, 6, and 5 in the processor status register.
These three bits set a priority level that inhibits granting of bus re-
quests on lower levels.
2. Bus requests from external devices can be made on one of five re-
quest lines. A non-processor request (NPR) has the highest priority,
and its request is honored by the processor between bus cycles of
an instruction execution. Bus request 7 (BR7) is the next highest
--priority, and BR4 is the lowest. The four lower level priority requests
are honored by the processor between instructions. When the pro-
cessor’s priority is set to a level, for example 6, all bus requests on
BR6 and below are ignored.
3. When more than one device is connected to the same bus request
(BR) line, a device nearer the central processor has a higher priority
than a device farther away. Any number of devices can be connected
to a given BR or NPR line.
Once’s device other than the processor has control of the bus, it is for one
of two types of requests: 1) NPR Request, 2) ‘Interrupt Request.
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