Specifications

Dvnamlc Master-tive #?e!&eM
astar-slave relationships are dynamic. The
,processor, for example, may p&s bus control to a disk. The disk, as master,
could then communicate with a slave memory bank.
Since the Unibus is used by the processor and all I/O devices, there is a
priority structure to determine which device gets control of the bus. There
fore, every device on the Unibus which is capable of becoming bus master
has a ‘Priority assigned to it. When two devices which are kapable of becorn-
ing a bus master request use of the bus simultaneously, the device with the
higher priority will receive control first. Details of what conditions must be
satisfied before a device will get control of the bus are given in the section
on System Interaction.
,+(A11 CENTRAL PROCESSOR-There are four major features which are of
particular interest to the programmer: l), the General Registers: 2), the
Processor Status Word; (3), the Addressing Modes; and 4), the Instruction
Set. The addressing modes and the instruction set of the PDP-11 processor
will be discussed in detail in Chapters 3 and 4.
‘Ganeral Registers-The KAll processor contains eight 16.bit general regis-
Ms. These eight general registers (referred to as RO, Rl, . . . . . R7) may
be used as accumulators, as index registers, or as stack pointers. One of
these registers, R7, is reserved as. a program counter (PC). Generally, the
PC holds the address of the next instruction, but it may point to data or
to an address of data. The register R6 has the special function of processor
stack pointer.
Central Processor Status Register-The Central Processor Status Register
(PS) contains information on the current priority of the processor, the result
of previous operations, and an indicator for detecting the execution of an
instruction to be trapped during program debugging. The priority of the
central processor can be set under program control to any one of eight.
levels. This information is held in bits 5, 6, and 7 of the PS.
Four bits of the PS are assigned to monitoring different results of previous
instructions. These bits are set as follows:
Z-if the result was zero
N-if the result was negative
.
C-if the operation resulted in a carry from the most significant bit
V-if the operation resulted in an arithmetic overflow
The T bit is used in program debugging and can be set or cleared under pro-
gram control. If this bit is set, when an instruction is fetched from memory
a processor trap will’ be caused by the completion of the instruction’s
execution.
Central Processor Status Register (PS)
CORE MEI;(ORy-The PDP-11 allows both 16.bit word and 8-bit byte ad-
dressing. The address space may be filled by core memory and peripheral
device registers. The top 4,096 words generally are reserved for peripheral
device registers. The remainder of address space can be used for read-write
core memory or read-only core memory.
Read-write core memory is currently available in 4,096 1Qbit word segments.
This memory has a cycle time of 1.2. microseconds and an access time of
500 nanoseconds. It is a standard part of a PDP-ll/PO system.
6