Specifications

INTR-lNTerRupt
This bus operation is initiated by a master immediately after receiving bus
control to effect a program interrupt in the processor. It proceeds as follows:
0.
::
::
- 5.
Device has become bus master via PTR and BBSY is as&ted.
Master puts interrupt vector address on D and asserts INTR.
Processor sees INTR and waits 75 nanoseconds (deskewdata).
Processor strobes data and asserts SSYN.
Master sees SSYN, drops INTR, -D, and BBSY. The master has now
relinquised bus control directly to the processor. The INTR sequence
is termed an active release of bus control.
Processor sees INTR drop and drops SSYN and. enters interrupt
sequence to update PC and PS.
1. Step 1 must be made simultaneously with step 8 of FTR; that-is, SACK cannot
be dropped until INTR i,s asserted.
2.’ When the processor’sees SACK drop. it waits 75 nanoseconds (deskew). If, at
that time, INTR = 1. the processor issues no SG’s until the interrupt sequence
is complete.
Figure D-4 shows the signals for the INTR operation.
~
SIGNALS Al MASTER
BBSY T
JR
DATA
IT
1
INTR
IT
SMN
rR 1
-%NALS AT FIWCESSOR
BBSY -i
UT
MTA
INTR
SBYN
-R
I
jR 1
IT
T. SIGNAL AS TRANSMITTED
R * SIGNAL AS RECEIVED
Figure D-4 INTR Operation
GENERAL NOTES ON THE BUS OPEliATlONS
1. A master device doing a read-modify-write operation must keep bus
control BBSY asserted for both bus transactions (both the DATIP
. and the DATO or DATOB). This is the one case where an NPR request
will not be honored between bus transactions.
2. A device becomes master by the PTR operation. If ‘the request for
bus control was made on the NPR line, bus control must be released
passively (by dropping BBSY). Bus control is then passed either back
to the processor to execute the next bus cycle of the instruction or
to another device requesting on the NPR tine. If a device becomes
master via a,BR request line, control may be passed actively back
to the processor by using the INTR operation or passively (by drop