Specifications

5.
6.
Master sees SSYN and waits 75 nanoseconds, minimum (data des-
kewing + internal gating deskewing).
Master.strobes data, drops MSYN, and waits 75 nanoseconds (des-
kew address).
7.
Masfer drops A and C and waits for SSYN to fall.
8.
Slave sees MSYN fall and drops SSYN and D lines.
9. Master sees SSYN fall, signaling-end of bus operation.
NOTES:
1. Step 1 of the next data transfer may begin at step 7 of the current DATI or
DATI P.
l
‘2. Step 2 of the next data transfer may begin at step 9 of the current DATI or
DATIP.
MT0 AND DATOB-These two bus operations transfer data out of the mas-
ter to the slave. DATO is used to transfer a word to the address specified
by A < 17:Ol >. The slave ignores A00 and the data appear. on D < 15:00 >.
DATOB is used to transfer a byte to the add<ess specified by A < 17:00 >.
A00 = 0 indicates the low byte and data appears on D < 07:OO >; A00 f 1
indicates high byte and data appears on D < 15:08 >. The sequence of op
eration is as follows:
1.
.
2.
3.
4.
2:
7.
Master puts address on A, data on D, 2 or 3 on C, and waits 150
nanoseconds (75 nanoseconds for deskewing address + 75 nano-
seconds for address decoding).
Master asserts MSYN.
Slave decodes address, sees 2 or 3 on C and MSYN and strobes in
word or byte. When slave has taken data, it asserts SSYN. If the slave
is a destructive read-out device and its pause flag is set (by DATIP),
slave begins write cycle; if .not, slave must first do a read cycle to
clear the memory cell and then a write.
Master sees SSYN and drops MSYN and waits 75 nanosecondi (des-
kew address).
Master drops A, D, and C, and waits for SSYN to fall.
e
Slave sees MSYN fall and drops SSYN.
Master sees SSYN fall, signaling end of bus operation.
Figure D-2 shows the signals for a DATO operation.
DATO
SIGNALS AT MAST&
.
DATA
I
MSYN
SSYN
IT
I
IT
IR
I
SIGNALS AT SLAVE
ADDRESS-CONTROL IR
I
BATA IR
1
MSYN
IR I
SSYN * ‘T
MEMORY CYCLE
-1
Figure D-2 DATO Operation
100