Specifications

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APPENDIX l+UNlBUS OPERATIONS
There are ‘six bus operations: four to effect data transfers, on9 to transfer
bus control, and one to effect a program interrupt. This appendix describes
the signal interaction on the Unibus to perform these six operations.
DATA TRANSFERS
The four data transfers use the C lines coded as follows:
Cl co
0 0 DATI-DATa In
0 1 DATIP-DATa In, Pause
1 0 DATO-DATa Out
1' 1 DATOB-DATa Out, Byte
DATI AND DATIP-These two bus operations transfer data from a Slave
whose address is specified by A < 17:Ol > into the master. Both transfers
are made in words on D, < 15:OC >. In destructive read-out devices,
DATI commands a read-restore operation, while DATIP commands a read-
pause operation and the setting of a pause flag. DATlPs are to be followed
by a DATO or DATOB to effect a read-modify.write data exchange. In non _
destructive read-out devices, DATI and DATIP are treated identically. The
sequence of operations is as follows:
1. Master puts address on A, 0 or 1 on C, and waits 150 nanoseconds.
(75 nanoseconds for deskewing address + 75 nanoseconds for ad-
dress decoding).
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2. Master asserts MSYN.
3. Slave decodes address, sees 0 er 1 on C, and MSYN and ldegins read
cycle (flip-flop register would simply gate flop outputs to bus).
4. Slave completes read cycle, outputs data to D lines, and asserts
SSYN. If the slave is a destructive read-out device, it now restores
data on a OATI: it sets a pause flag on a DATIP.
Figure D-l shows the signals for a DATI operation.
a
SIGNALS Al MASTER
ADtRESS-CONTROL AT !
I
DATA
jR
MSYN
JT
L .
SSYN
IR
SIGNALS AT SLAVE
ADDRESS-CONTROL
IR 1
DATA p T
I
I
MSYN
IR I
SSYN
MEMORY CYCLE
I
T= SIGNAL AS TFIANSMITTEO
,
R*SIGNAL AS RECEIVED
Figure D-l DATI Operation
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