Specifications

SUBROUTINE CALL: JSR reg,dst
1 JSR Jump to SubRoutine
(dstb (tmp), 0%) J
(PC> + (w3), Ww) + (PC)
SUBROUTINE RETURN: RTS reg
RTS ReTurn from Subroutine
(w) + PC. t (w3)
SINGLE OPERAND GROUP: OPR dst
CLR(B)
< COM(B)
INC(B)
DEC(B)
NEG(B)
ADW)
SBC(B)
TST(B)
ROR(B)
ROL(B)
A5R( B)
ASL( B)
JMP
SWAB
CLeaR (Byte)
0 + (dst)
COMplement (Byte)
- (dst) + (dst)
INCrement (Byte)
(dst) ,+ 1 + (dst)
DECrement (Byte)
(dst) 1 i 4 (dst)
NEGate (Bvte)
+‘(dstj + 1 + (dst)
ADd Carry (Byte)
(dst) + (Q --, (dst)
SuBtract Carry (Byte)
(dst) - (C) + (dst)
TeST (Byte)
0 - (dst)
Rotate Right (Byte).
- rotate right 1 place with C
ROtate Left (Byte)
rotate left 1 place with C
Arithmetic Shift Right (Byte)
shift right with sign extension
Arithmetic Shift Left (Byte)
shift left with lo-order zero
.063DD 4’4 r/ 4 2.3”
JUMP OOOlDD - 1.2
GM) + (PC)
SWAP Bytes
0003DD ,.‘t/OO 2.3 _
bytes of a word are exchanged
004RDD -
4.2
00020R -
3.5
.050DD 1000 2.3
-051DD 4 400 2.3
-052DD
.053DD
.05,4DD
.055DD
.056DD
.057DD
.060DD
.061DD
.062DD r’ r’/ d 2.3”
.
CONDITION CODE OPERATORS: OPR
1.5
Condition Code Operators set or clear combinations of condition code bits.
Selected bits are set if S = 1 and cleared otherwise. Condition code bits cor-
responding to bits set as marked in the word below are set or cleared.
CONDITION CODE OPERATORS;
- 0 0 0
1 I
1 I I
2
I I i
4SNZVC
15 54324 0
Thus SEC ‘= 000261 sets the C bit and has no effect on the other condition
code bits (CLC = 000241 clears the C Bit)
OPERATE GROUP: OPR-
HALT HALT 000000
processor stops; (RO) and the HALT address in lights
l.8 I
WAIT WAIT
00000 1 1.8
processor releases l&s, waits for interrupt
92