Specifications

to identify an interrupt, since the interrupt servicing hardware selects and
begins executing the appropriate service routine.
The device’s interrupt priority and service routine priority are independent.
This allows dynamic adjustment of system behavior in response to real-time
conditions.
The interrupt system allows the processor continually to compare its own
priority levels with the levels of any interrupting devices and to acknowledge
the device with the highest level above the processor’s priority level. Servic-
ing an interrupt for a device can be interrupted for servicing a higher priority
device. Service to the lower priority device can be resumed aUtOmaticallY
upon completion of the higher level servicing. Such a process, called nested
interrupt servicing, can be carried out to any level.
Rentrant Code-Both the interrupt handling hardware and the subroutine
call hardware are designed to facilitate writing reentrant code for the
PDP-11. This type of code allows use of a single copy of a given subroutine
or program to be shared by more than one process or task. This reduces,the
amount of core needed for multi-task applications such as the concurrent
servicing of many peripheral devices.
General Register-The PDP-11 is equipped with eight general registers. All
are program-accessible and can be used as accumulators, as pointers to
memory locations, or as full-word index registers. Six registers are used for
general-purpose access while the seventh and eighth registers are used as
a stack pointer and program counter respectively.
Instruction Set-An important feature of the PDP-11 instruction set is the
availability of double operand instructions. These instructions allow memory-
to-memory processing and eliminate the need to use registers for Storage of
intermediate results. By using double operand instructions, every memory
location can be treated as an accumulator. This significantly reduces the
length of programs by eliminating load and store operations associated with
single operand machines.
Addressing-Much of the power of the PDP-11 is derived from its wide range
of addressing capabilities. PDP-11 addressing modes include list sequential
addressing, full address indexing, full 16qbit word addressing, 8-bit byte
addressing, stack addressing, and direct addressing to 32K words.
Variable length instruction formatting allows a minimum number of bits to
be used for each addressing mode. This results in efficient use of program
storage space.
Asynchronous Operation-The PDP-11’s memory and processor operations
are asynchronous. As a result, I/O devices transferring directly to or from
memory may steal memory cycles during instruction operation.
PACKAGING ’
The PDP-11 has adopted a modular approach to allow custom configuring Of
systems, easy expansion, and easy servicing. Systems are composed of basic
building blocks, called System Units, which are completely independent sub-
systems connected only by pluggable Unibus and power connections.
There is no fixed wiring between them. An example of this type of subsystem
is a 4,096-word memory module.
System Units can be mounted in many combinations within the PDP-11
hardware, since there are no fixed positions for memory or l/O device con-
trollers. Additional units can be mounted easily and connected to the system
2
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