alMml digihl equipmentcorpomtion
Digital Copyright 1969 by Equipment Corporation PDP is a registered of Digital Equipment, trademark Corporation The material in this handbook is for information purposes only and is subject to change without notice.
TABLE OF CONTENTS CHAPIER PDP-11 1 lNTRODUCTlOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .:.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1 . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . , . . . . . . . . .. . . . . . . . . . . . . . . . 1 SYSTEMS UNIBUS KAl 1 PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . DOUBLE OPERAND-INSTRUCTIONS .......................... i.. ............... 17 Arithmetic Operations .................. 1........................................ Boolean Instructions ............................................................. BRANCHES .......................................................................... .:. ..... Unconditional Branch .......................................................... I Simple Conditional Branches ..............................................
. \ TELETYPE CONTROL (MODEL KLll) ......................................... Teletype Control .......................................................... r ....... Keyboard/Reader Operation ................................................ Registers (TKS, TKB) .................................................. Teleprinter/Punch ................................................................ Registers (TPS, TPB) .................................................... Programming Example ........................
UNIBUS CONTROL ............. ’......................................................... Priority Arbitration ................................................................. .............................................. Selection of Next m m Interrupt Sequence ................................... . .......................... Example of Interrupt, etc. .................................................. Example of NPR Operation ..................................................
INSTRUCTION FORMATS APPENDIX C-ADDRESS APPENDIX D-UNIBUS ._.___...........___........................................ MAP . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . OPERATIONS .......... ........ ............ ........ .. 95 97 99 DATA-TRANSFERS .__............._._..................................................... 99 DATI and DATIP . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The PDP-11”is available in two versions-PDP-ll/lO and PDP11/20. The basic PDP-ll/lO contains 1,024 words of read only memory in conjunction with 128 words of read/write memory and the basic PDP-ll/PO includes 4,096,words of read/write memory.
CHAPTER 1 INTRODUCTION This publication is a handbook for Digital Equipment Corporation’s PDP-11. It provides a comprehensive overview of the system structure, the instruction repertoire, input/output programming, peripherals, general interfacing, software, and console operation. PDP-11 is Digital’s answer to the demand for a modular system for real-time data acquisition, analysis and control.
to identify an interrupt, since the appropriate begins executing the interrupt servicing service routine. The device’s interrupt priority and service This allows dynamic adjustment of system conditions. hardware selects and routine priority are independent.
in the field. In case maintenance is required, replaced with spares and operation resumed -E defective System Units can be within a few minutes.
All PDP-11 processors, memories and peripherals are electrically and mechanically modular subsystems .supported in System Units. which are simply plugged together to form a computer tailored to user needs.
I CHAPTER i SYSTEM SYSTEM INTRODUCTION DEFINITION Digital Equipment Corporation’s PDP-11 is a 16.bit, general-purpose, parallellogic computer using two’s complement arithmetic. The PDP-11 is a variable word length processor which .directly addresses 32,768 16.bit words or 65,536 8-bit bytes. All communication between system components is done on a single- high-speed bus called a Unibus. Standard features of the system include eight general-purpose registers which can be used as accumulators.
Dvnamlc Master-tive #?e!&eMastar-slave ,processor, for example, could then communicate relationships are dynamic. The may p&s bus control to a disk. The disk, as master, with a slave memory bank. Since the Unibus is used by the processor and all I/O devices, there is a priority structure to determine which device gets control of the bus. There fore, every device on the Unibus which is capable of becoming bus master has a ‘Priority assigned to it.
Read-only core memory (ROM) is available in 1,024 16 bit-word segments. The access time of the ROM is 500 nanoseconds. Memory is also available in 128 16-bit word segments with a 2.0 microsecond cycle time. Both 1,024 words of read-only memory and 128 words of read-write memory mount in a single System Unit and are a standard part of the PDP-ll/lO system. PERIPHERAL DEVICES-The ASR-33 Teletype with low-speed paper tape reader and punch is provided in the basic PDP-11/20 system. Options for the .
NPR Requeata-NPR data transfers can be made between any two peripheral devices without the supervision of the processor. Normally, NPR transfers are between a mass storage device, such as a disk, and core memory. The structure of the bus also permits device-to-device trat’ISfer% allowing. customer-designed peripheral controllers to access other devices such as disks directly. An NPR device has very fast access to the bus and can transfer at high data rates once it has control.
Priorities permitting, the processor relinquishes the bus to that device. When the device has control of the bus, it sends the processor an interrupt command with the address of the words in memory containing the address and status of the appropriate device service routine. The processor then “pushes”first, the current central processor status (PS) and then, the current program counter (PC) onto the processor stack. The new. PC and PS (the “interrupt vector”) are taken from the location specified by the.
5. 6. 7, 8. service routine is begun. Note that those operations all occur automatically and that no device-polling is required to determine which service routine to execute. 7.2 microseconds is the time interval between the central Processor’s receiving the interrupt command and the fetching of the first inStruCtion. This assumes there were no NPR transfers during this time.
CHAPTER 3 ADDRESSING jdODES‘ Most data in a program is structured in some way-in a table, in a stack, in a table of addresses, op perhap$ in a small set of frequently-used variables‘ local to a limited region of a program. The PDP-11 handles these common data structures -with addressing modes specifically designed for each kind of access. In addition, addressing for unstructured data is general enotfgh to permit direct random ac%ess to all of core.
Deferred register OPR (R). addressing INDEXED AD~RE&G-T~IZ jr&en to per&t random tions of the form specify indexed and the contents may also access in PAL-11 by the form general fegisters may be used as index reg of items in tables or stacks of data. InStrUC- mode addressing. of the specified The index word containing be selected OPR X(R) The effective general- register X follows address R. the instructi& is the sum of X word.
(decrement by two) address ister as the operand address. specify autodecrement dressing is and-uses the new contents Instructions of the form -0PR -(RI addressing. The address field of the general for autodecrement This mode also may be deferred and specified by instructions OPR @ -(R).
tion word may be taken as the address of an operand by specifying in immediate mode addressing. That is, instructions of the form refer to the operand at, address this form into an address field followed by a word containing A. PAL-11 assembles address deferral cxprwssions of the o erand address. P MUTmE ADDRESSIF&-Relative addressing specifies the operand address relative to the instruction location. This is accomplished by using the pc as an index regkter. The PC is considered as a base address.
and is followed by index words and immediate operands for the source and destination address fields as appropriate. Source address calculations are performed before destination address calculations. Since each operand may be anywhere in core storage or in the general registers, each memory location is thus effectively provided with the arithmetic capabilities of an accumulator.
CHAPTER 4 INSTRUCTION SET This chapter Presents the order code for the PDP-11. Each PDP-11 instruction is described in terms of five parameters: operation, effect on condition Special codes, base timing, assembler mnemonics, and octal representation. comments are included where appropriate.
Arithmetic Operations- Operation: (src) + (dst) Condition Codes: Z: set if (src) = 0; cleared N: set if (src) < 0; cleared C: not affected V: cleared otherwise otherwise Description: Moves the source operand to the destination vious contents of the destination are lost. The contents not affected. The MOV instruction is a generalization of ‘load,” “pop,’ and interregister transfer operations. General registers may be loaded instructions of the form: location.
Description: Adds the source operand to the destination operand and stores the re< at the destination address. The original contents-of the destination are lost. Ttr, ktmcI of the sowe are not a#ectod. Two’s cwpt addition is perfoti. The ADD instruction inckdes as special cases the “add-to-register,” memory,” and ‘Md-reister-to-rwister” functions: Add-to&gister ADD WC, R , ADD R, +t A&l-to*mory Add Register-to-Register ADD RA. RB Arithmetic instruction may also ADD .
WC 2 01 I I 12 (5 .Operation: Condition I compares The only Boolean Instructions-These double operand arithmetic bit level. 1 1 I I I t 0 5 BIS 5 the source and destination operands. action is to set the condition codes instructions group. They Bll set , 1 6 Description: Arithmetically Affects neither operand. appropriately. have the same permit operations format- as the on data at the 2.31~~ src.
Bll Test * BIT 0, WC I . 15 I 12 Operation: .2.9*** rrc,dst 3 I I I I I 11 dd I 6 , 1 I 5 0 (src) A (dst) Condition Z: N: C: V: Codes: set if result = 0; cleared otherwise set if high-order bit of result set; cleared not affected cleared otherwise Description: Performs logical “and” comparison of the source and destination operands and modifies condition codes accordingly. Neither the source nor destination operands are affected.
gbnpk corldttbnrit Bran&es-Conditioned branches combine tion a conditional sMp, unconditional branch sequence. in one instruc- . Timing for the conditional dition is not met, followed a program branch occurs). branches is shown as execution time if the con-. by the execution time if the condition is met (end Branch on Eauol(z.ro) 0 , ,O BEQIOC I I I I 4 I 15 ~.SILS,~,~.
Operation: lot + (PC) if N = 0. Description: Tests the state of the N-bit and causes BPL is the complementary operation to BMI. Branch on Carry 1 , Set BCS 0, , 31 lot if N is,clear. 1.5~s I4 I t5 Operation: a branch 8 I I I I ,Z.
largest .. ......... .... . . . . . . . . . . . . 077777 077776 . . . positive 000001 000000 177777 177776 negative lQo00l smallest whereas in unsigned 100000 16-bit arithmetic highest the sequence is considered to be . . . . . ~. . . . . . . . . . . . . . . . . . . . . . . . . 177777 . 000002 00000 1 _. .._. . . . _.. ._ ,. .___, 000000 lowest Branch on Less 01 BLT ThadZero) 0 I 2 I I 15 l.Sir. lot II 4 I 8 I offset I I I 2.
Branch on Less than or 01 to, Equal(Z*ro) BLE 1.5~~. lot I ‘31 14 offset t I I 2.6~ I I 0 07 i5 Operation: lot + (PC) if Z v (N V V) = 1 Description: Operation of BLE is similar to that of BLT but in addition cause a branch if the result of the previous operation was zero. Branch on Greater 0, 15 Than I 0 Operation: (Zero) I BGT 3 I II 1.51u,2.
Branch BLO on LOwn t.5 YS, 2.6~s IOC Offset t 1 95 Operation: Description: 0, 1 , 3 , 1 4 e I I I I I 1.1 7 0 lot + (PC) if C = 1 BLO is the same instruction as BCS q The following example illustrates the use of some of the instructions and addressing modes described thus far. Two new instructions are used: INC (INCrement) and ASL (Arithmetic Shift Left) which respectively, add 1 (INC) and multiply an operand by 2 (ASL). Their operation is fully described later in this chapter.
address. A “boundary error” condition will result tempts to fetch an instruction from an odd address. Deferred address when the processor at- index mode JMP instructions permit transfer of control to the contained in a selectable element of a. table of dispatch vectors. SUBROUTINES-The subroutine call in the PDP-II provides for automatic nesting of subroutines, regntrancy, and multiple entry points.
ReTurn from 3.5&S Sutwoutine I 15 Operation: Condition 3 2 0 (reg) + (PC) T (ret3 Codes: not affected Description: Loads content of reg into PC and pops the top element Processor stack into the specified register. Execution time for RTS to the basic instruction time. is of the. equal Return from a subroutine is typically made through the same register that was used in its call.
The instruction INC Rl increases CLR RO zeroes the register RO the contents of Rl by 1 and the instruction 2. Saving and restoring registers on the stack-This RO-R5 onto the stack. It is called by: JSR R5, SAVE MOV R4, -(SP) MOV R3, -(SP) SAVE: \ MOV R2, -(SP) MOV Rl, -(SP) MOV RO, -(SP) JMP R5 is equivalent to comparing the operand TST opr = CMP opr, #0 The only effect is to set the appropriate condition codes. REST: The operation it is used, the call to REST.
At this program. point execution of RTS PC returns control to the main A character is typed in DECTY by loading the teleprinter buffer (TPB) and waiting for the teleprinter READY flag, the most significant bit of the low-order byte of the teleprinter status word (TPS), to be set. The symbols CR and sentations for carriage LF are assumed equal to the return and line feed respectively. This’subroutine types the unsigned the use of stacks. , DECPNT: DECREM: integer MOV #lo.
TYPFIN: ;suspend processor opera;tion, wait for key continue ;get address of bad item: ;initialization entry ;address of array ;-length of array ;high limit ;low limit ;Z-bit is set if no more out ;of limits ;an element is out of limits, ;save registers ;RO holds address + 2, get ;operand into RO Tprint out number ;type CR, LF mote use of second entry ;point ;restore registers ;continue searching array, ;alternate entry ;another bad element? Operand Instructions are repre- HALT JSR R5, TOLER TYPOUT: -
DECrment 01 DEC drt 10, I 15‘ 2.3~ I 13, I 6 15 Operation: (dst) - Condition 2: set N:-set V: not C: set Subtracts 1 from the contents NEG 1 I 0 I 5 of the destination. 2.
Multiple Precision Operations-It is sometimes on operands considered as multiple words.‘The vision for such operations with the instructions (SuBtract Carry). ADC dst ADd carry 01 IO, 1 5 I I I 5 I convenient to d6 arithmetic proADC (ADd Carry) and SBC PDP-11 makes special 2.3YS dst 1 1 6 15 Operation: (dst) + (F) + (dst) Condition Cobes: Z: set if result N: set if result c: set if (dst) wise V: set if (dst) wise.
ROtaA ROR Right 2.3~ dst dst 01 15 Condition lOI I I 6 I .I 0 , I 6 Codes: I I I 1 5 0 Z: set if all bits of result = 0; cleared otherwise. N: set if the high-order bit of the result is set; cleared otherwise C: loaded with the low-order bit of the destination V: loaded with the Exclusive OR of the N-bit and C-bit (as set by the completion of the rotate operation). Description: Rotates all bits of the destination right one place.
- Arithmetic Shift ASR Right 2.3 us dst dst 01 , 0, 1 , 6, 1 , 2 15 Condition . , I 6 t e I 0 Z: set if the result = 0; cleared N: set if the high-order bit of otherwise C: loaded from the low-order V: loaded from the Exclusive .(as set by the completion,of Codes: I 5 otherwise the result is set; cleared bit of the destination OR of the N-bit and C-bit the shift operation) Shifts all bits of the destination right one ‘place. Bit 15 is rePlicated.
Double precision norma’lization ASL ROL DNORM: BVC ROR BR \ TST BNE ROR ASR :. . DNDONE: similarly: ; double A0 Al DZERO DNORM Al DNDONE A0 DN0RM Al Al BEQ DZERO: proceeds , precision left shift ; high order result O?. if so, check.
Operation: (src) + (dst) Condition Codes: Set on the byte result as in MOV Description: Same as MOV instruction. The MOVB instruction in register mode (unique among byte operations) extends the most significant bit of the byte register (sign extension). Otherwise MOVB operates on bytes exactly as MOV operates on words. Coware Byte ‘I I CMPS 12 t5 Operation: (src) - Condition -I 12 src,dst src I 1 2.
LNLINE is the Length EDIT: of uNpacked LINES. The routine MOV # INSTRING, RO MOV #OUTSTRING, Rl MOV #EOLCHAR, R2 MOV #SPCHAR, R3 MOV #LNLINE, R4 MOVB (RO) + ,R5 CMP R5, R2 BEQ FILINE CMP R5, R3 BEQ NXTCHR DEC R4 MOVB R5, (Rl) + BR NXTCHR CLRB (Rl) + DEC R4 BNE FILINE CMPB (RO), #EORCHAR BNE NULINE NOLINE: NXTCHR: FILINE: CHKEND: Single Operand CLeaR requires 24 words. ; set up input byte pointer ; set up output byte pointer ; put high use constant in reg.
~. NEGote Byte NEGB 23ns -dst dst ‘I 101 I Ii, I 141 I I5 6 I I t 5 -. 0 l Operation: -(dst) Condition + (dst) in detail, - ; (dst) f. 1 + (dst) Codes: Set on the byte result as NEG Description: Same as NEG. T&T TSTB Byte 2.3~(1* dst dst ‘I 15 I I 17, 6 Operation: 0 - Condition 5, lOI I 0 (dst) Codes: Set on the byte result as TST Description: Same as TST. cohtp*m(Hlt Byte ‘I 101 I COMB 151% dst I 2.
, . mtate Left Byte ROLB drt ’ 2.3~1 Q ~ I I t 1 I I .I 1 1 1 ’ ’ 1 dst 1 15 , 0 6 3 6 Operation: as in ROL on byte operands Condition Codes: set on the byte results Description: 0 as ROL Shift 1 1 Riaht Bvte 0 I ASRB 16’1 2.3~7 dst I I 2 I I 6 15 Operation: 0 5 as in ASR on byte operands ConditionCodes: Description: set on the byte result as ASR Same as ASR Arithmetic Shift ‘I Left Byte 101 I ASLB I ‘61 dst I 2.
Combinations of the above set or clear operations may be ORed together to form new instruction mnemonics. For example: CLCV = CLC ! CLV. The new or” in PAL-11.) instruction clears C and V bits. (‘I!” signifies “inclusive MISCELLANEOUS RESet CONTROL ExTernol 01 IO, iNSTRUCTIONS 20 ms RESET bus I 101 I 101 I lOI I I 5 , 0 15 Condition Codes: not affected Description: Sends an INIT pulse along the Unibus devices on the bus are reset to their state at power-up. by the processor.
EMulotw EMT Traps ‘I 101 ,4, 0, 15 9 Operation: (PS) J, WI J (30) + (3?) + Condition 9.9 us xycx , 1 , XXI , 1 , , 7 0 SP SP PC PS Codes: loaded from trap vector. . Description: Performs a trap sequence with a trap vector address of 30. All operation codes from 104000 to 104377 are EMT calls. The low-order byte, bits O-7 of the EMT instructions, may be used to transmit information to the emulating routine (e.g., function to be performed). The trap vector for EMT is at address 30.
R.Turn / from 01 Interrupt ,o, 4.Bus RTI I IO, I 101 I 101 I a21 0 IS Operation: SP T (PC), SP t Condition Codes: loaded from (PS). processor stack. Description: Used to exit from an interrupt or TRAP service and PS are restored (popped) from the processor stack. routine.
An instruction that again has no effect. set the T-bit-Since An instruction that caused an sprung and the entire routine for routine exists with an RTI or in word, the T-bit is set again, the is executed and, unless it ,is one trap occurs. An instruction that the T-bit was already set, Settiflg it Instruction Trap--The instruction trap is the service trap is executed.
CHAPTER ADDRESS 5 ALLOCATION The PDP-11 provides for a very flexible addressing structure. Both 16-bit words and 8-bit bytes can be directly addressed. Addresses are 1Bbits long allowing for direct addressing of 32,768 words or 65,536 bytes. ADDRESS MAP As a result of the organization functions. A map of possible of the PDP-11, bus addresses serve several PDP-11 bus address allocation is shown CONTENT BUS ADDRESS 0 Program Processor 4608 Processor.
in Figure 5-1. Three areas of addresses of particular interest to the Programmers are: 1) Interrupt and Trap VeMors; 2) Processor Stack and General Storage; and 3) Peripheral Device Registers. INTERRUPT AND TRAP VECTORS-Addresses location 4001 are generally reserved for interrupt between lOCatiOn and trap vectors. zero and PROCESSOR STACK AND GENERAL STORAGE-Addresses between 4001 and the limit of implemented core are available for the processor stack or other programs and data.
CHAPiER 6 PROGRAMMING OF PERIPHERALS Programming of peripherals is extremely simple in the PDP-11-a special class of instructions to deal with input/output operations is unnecessary. The Unibus permits a unified addressing structure in which control, status, and data registers for peripheral devices are directly addressed as memory locations.
devices. Many devices will require less than sixteen status bits. Other devices will require more than sixteen bits and therefore will require additional status and control registers. Device Function Bits-These three bits specify operations that a device iS to perform. An example of one operation for a paper tape read&r is read one character. For a disk one operation would be read a block of words from memory and store them on the disk.
acter. Incrementing read. The instruction performs that more word. the function. PRS will set bit 0 and cause one character PRS INC MOV #l, PRS does the same thing but takes to be one DATA BUFFER REGISTERS-Each device has at least one buffer register for temporarily storing data to be transfer into or out of the computer. The number and type of data registers is a function of the device. The paper tape reader and punch use single 8-bit data buffer registers.
A tvoical _. 1. 2. 3. 4. set might be: Control-and status register Memory address register Word count register Device address register Loading the device address register would in general initiate the transfer, which then proceeds without processor intervention. The device issues nonprocessor requests for the Unibus that, when granted, allow direct data transfer between the device and memory. These requests are interleaved with processor. requests for the bus.
ReTurn fmm Interrupt instruction is used to reverse the action of the interrupt sequence. The top two words on the stack are popped into the PC and PS, returning control to the interrupted sequence. PROGRAMMING A EXAMPLE paper tape reader interrupt service could appear as follows: First the user must initialize the service routine by specifying an address pointer and a word count ; set up address pointer INIF MOV #BUFADR, #0 ; in third word of MOV instruction. POINTR = .
The DIGITAL M225 module contains 8 high speed general-purpose registers. The M225 general registers provide program flexibility when used as accumulators, index registers, and pointers to data words.
CHAPTER TELETYPE (MODEL 7 LT33-DC/DD) The standard Teletype Model 33 ASR (Automatic Send-Receive) can be used to type in or print out information at a rate of up to ten characters per second, or to read in or punch out perforated paper tape at a ten characters per second rate. Signals transferred between the 33 ASR and the control logic are standard serial, 11-unit code Teletype signals.
Teletype unit to release the tape feed latch. When releasea the latch mechanism stops tape motion only when a complete character has been sensed, and before sensing of the next character is statthd. When the character is available in buffer (TKB), the busy bit (BUSY) i$ cleared and the done flag (DONE) is set. If the interrupt is enabled, a request is made for the bus at level 4 (BR4). The interrupt vector is at location 60,.
Registers Teleprinter Status Word (TPS) 7 6 2 * L I- I 1 0 0 IN-f L EN6 READY Bit 2 MAINT 6 INT ENB 7 READY Teleprinter Maintenance function which connects TPB serial output to TKB serial input. the Teleprinter to O-No interrupt; 1 -attaches the priority interrupt system at BR4. Set by punch/printer DONE; cleared by loading the teleprinterbuffer (TPB). Buffer (TPB) I 15 8 PRDGRAMMING EXAMPLE-To the printer: ECHO: INC TKS c TSTB TKS BPL .-2 TSTB TPS BPL .
by setting a DONE bit. If the interrupt is enabled and the interrupt is granted, the processor traps to location 70, and may immediately begin executing the service routine for the paper tape reader. Reghters Paper Tape Reader Status Word (PRS) 15 11 7 0 0 l- 6 0 0 0 it * L ERROR Bll * 0 L BUSY LINT L EN6 DONE ROR RDR ENB ~ 0 RDR ENB Requests bus only 6 INT ENB O-No interrupt; 1-attached to priority interrupt system at BR4.
Registers Paper Tape Punch Status Word (PPS) Bit 6 INT ENB O-No Interrupt; l-Attached fo priority iflterrUFt system. (Note: An interrupt occurs when 1NT EN8 is a 1 and either the ERROR flag or the READY flag i becomes a ‘1.) 7 READY 15 ERROR Set by punch done; cleared tape punch buffer (PPB). Error Flag-Set by out-of-tape off switch.
ENVIRONMENTAL 55”-100°F 20% -95% MODEL PC11 PCllA PRll RH (without ~- condensation) POWER REQUIREMENTS 115+10% 60 Hz 115+-10% 50 Hz 115-c10°h 50-60 Hz DESCRIPTION Reader, Punch & Control Reader, Punch &Control Reader 81 Control LINE FREQUENCY KWll-L) CLOCK (TYPE The KWll=L real timeclock provides a method of measuring time intervals at line frequency. This clock consists of a frequency source and control logic. When enabled the clock causes an interrupt every 16.
CHAPTER DESCRIPTION -~ 8 OF THE UNIBUS Communication between all system units in a PDP-11 configuration is done by a single common bus: the Unibus. All communication-both instructions and logical operations-is defined by a set of 56 signals. This set of 56 sig nals is used for program controlled data transfers, direct memory data transfers, priority bus control, and program interrupt. This chapter presents the concepts of the Unibus and how they affect proand interfacing hardware.
the bus to communicate with other devices, call,ed slaves, on the bus. An example of this relationship is the processor (master) fetching an instruction from memory (which is always a slave). INTERLOCKED COMMUNICATION-For erich control signal issued by the master device, there is a response from the slave; thus bus communication is independent of the physical bus length and the response time of the master and slave devices.
oooo#O-017777 trt El . scFrwAF& AOORESS HAROWARE oooooo-own7 4K MEMORY ADDRESS BANK 02CWO-037777 02ooOO-037777 2nd 4K MEMORY 0Aw I I I I t40000-t57777 t40000-157777 7th MEMORY 4K BANK _ 760000-777777 t6oooo-t77777 PERIPHERAL BANK El Figure 8-2 Address . Map The peripheral bank is composed of the processor’s fast register, console switch register, and all device registers.
device. A data transfer from processor to memory (always out,” and a transfer from memory to processor is “data in.” TYPES OF DATA TRANSFERS-The master and slave is determined a slave) is “data type of data transfer being made between _ by the C lines coded as follows: DATO AND DATOB-The DATO and DATOB operations are used to transfer data out of the master to the slave. DATO is used to transfera word to the address specified by A < .17:01 >. The slave ignores A00 and the data ap pears onD < 15:00>.
I instruction sequence coding appears as: will leave 10027 in location 500. 1000: 105210 1002: 062710 ;INCB @RO ;ADD (PC)+, 000003 ;3 1004: In binary 200: This instruction The processor CMPB is assembled 200: 202: 204: compares is 177560 Dais Transferred 105210 _ 010923 000024 062710 000003 010024 010027 on D < 15:OB >; the contents of the Teletype with the ASCII value for the @#177560, #301 in three words as follows: 123727 177560 000301 will execute Processor Cycle 1.
\ MASTER OPERATION: A.C,D MSYN ‘4 rg------ A’C’D SLAVE DAl-0 SSYN 3 SSYN I Figure 8-4(a) The flow of signals for DATI is shown in Figure 8.4(b). (DATIP is similar except that the internal operation of the slave device is modified.) The master sets Control for DATI, sets Address for the slave to be se’lected, and asserts MSYN. The selected slave responds by setting Data for the information requested and asserts SSYN.
cessor granting status register. These three bits of bus requests-on lower levels. set a priority level that inhibits Second, bus requests from external devices can be made on oni of five request lines. NPR has the highest priority, and its request is honored by the processor between bus cycles of an instruction execution. BR7 is the next highest; BR4 is the lowest.
by negating BBSY. Bus control will then pass to either a device that was selected in the meantime by another PTR sequence or back to the processor, which will continue where it was interrupted. Active release of bus control is realized through the INTR bussequence. The INTR (interrupt) operation is used by the bus master to transfer to the processor a memory address (called the interrupt vector).
program would set certain function bits in the disk’s command register that specify a read or write function. For this example, disk was set to read. * and status assume the Once the disk’s control registers are initialized, the disk control logic’starts a search for the requested data. (fhe processor in the meantime has continued in its program execution.) When the disk has found the data, it assembles the first l&bit word from the disk surface into its data register.
, ,I ; . . The plug-in console board with modular construction is supplied in the basic 11/20 configuration. In addition to aiding programming, console contributes to ease of maintenance on the PDP-11.
CHAPTER 9 Interfacing A typical device bus interface as shown in Figure 9-l is composed of five major components: 1). Registers; 2), Bus Drivers and Receivers; 3). Address Selector; 4). interrupt Control; and 5), Device Control Logic. REGISTERS Each device is assigned bus addresses at which the program can interrogate and/or load the device status, control, and data registers. The standardized mapping for these registers and the bit assignments of the corn- .
I I I I I I I I L- M930 --- -J i WI-DRIVER Rl , R2=190fi R3. R4 = 390A 5% 1/4W 5% iI4W Figure 9.2 Typical Unibus Line Information is received from the bus using gates which have a high input impedance and proper logic thresholds. High input levels must be greater than 2.5 V with an input current less than 160 pa. Low level input must be less than 1.4 V with an input current greater than 0 pa.
Ml05 ADDREsS SELECTOR Tho ‘Ml05 Address Selector as shown in Figure 9-6 is used to provide gating signals for up to four device registers. The selector decodes the 18-bit bus address on A < 17:00 > as follows: Figure Figure 9.3 9.
. Figure 9.5 M785 Unibus Drivers and Receivers A00 is used for byte control. A01 and A02 are decoded to provide one of four addresses. A < 1203 > are determined by jumpers on the card. When the jumper is in, the selector will look for a 0 on that address lineA < 17:13 > must all be l’s-(this defines the external bank). Other bus inputs to the selector are C < 1:0 > and MSYN. The single bus output is SSYN. The user signals are SELECT 0.
EXT. CAP I -J f , 1 1 SELECT 2 H t A62L EH J 4 H SELECT 6 Ii I A61 L AmL GIL CaL SELECT I OUTHl6HH OUT LW IN tl a Figure 9.6 Ml05 Address Ii Selector 4 M782 INTERRUPT CONTROL The M782 Interrupt Control module contains the necessary logic circuits to allow a peripheral device to gain bus control and perform a program interrupt. The three circuits on this card are block diagrammed in Figure 9-8.
. -i I L--- Figure 9.7 -- ------2 Typical Peripheral 74 Device Regker .
In addition to two Master Control circuits, a third logic network provides the necessary signals and gating to perform the INTR bus operation. When either of the START INTR signals is asserted, the INTR bus signal is asserted along with a vector address qn D < 07:02 >. Bits 07:03 are determined by jumpers on the card. A jumper “in” forces a 0 in that bit. Bit 2 is controlled by Vector Bit 2. When the processor responds to the INTR signal by asserting SSYN, the INTR DONE signal is asserted.
, DEVICE CONTROL LOGIC The type of control logic for a peripheral depends on .the nature of )h” device. Digital offers a wide line of general-purpose logic IllO~Ul~S for IITF plementing control logic. These modules are described in detail In another Digital publication: The Logic Handbook. Figure 9.9 Typical‘lnterconnection of M782 Interrupt Control . 76 .
CHAPTER 10 CONFlGURATtON AND INSTALLAflON MODULAR PLANNING CONSTRUCTlbN Physically, the PDP.11 is composed of a number of System Units. Each System Unit is composed of three 8-slot connector blocks mounted end-toend as shown in Figure 10-l. The Unibus connects to the System Unit at the lower left and at the upper left. Power also connects to the unit in the leftmost black. A System Unit is connected to other System Units only via the Unibus. UNIBUS CONNECTION p:*~~ Figure 10.
+ + For 115 V standard, 3prong; U-ground, 15-ampere connectors For 230 V pigtail leads on one end 3. Cooling Fans 4. Filter 5. Programmers Console Approximate Size-11" layout of this unit. high, with 11/20 or Turn-Key Console 26” wide, 24” Figure deep. with ll/lO 10-2 shows the I * Figure 10.2 Approximate . Power-12OV Weight-100 Table Top PDP-11 Dimensions Ibs. (including +- 10%,47-63 Hz and H720-A) 230V -c 10%,47-63 Hz (BAll-CC and H720.B) CP, console and 4K core) 6 amps.
. Approximate Power-12OV Weight-90 Itis. (including zflO%,47-63 Hz @All-C5 and H720-A) 230V +10%,47-63 Hz (BAll-C5 and H720-B) ~ Figure 10.3 Figure 10.5 CP, cdnsole 6 amps. X 3 amps.
PDP-11TABLETOP UcFENSfdh MOUNTING BOX (BAll-EC)-The tabletop Extension Box is supplied, when ordered, for mounting of up to 6 additional System Units which can not be contained in the Basic Mounting Box. This unit is supplied with: 1. 15' of power cord with ground wire + For 115 V standard, 3-prong, U-ground, 15-ampere connector + For 230 V pigtail leads on one end 2. Cooling Fans 3. Filter 4. Front Panel 5.
10. H955)-D Mounting 11.. H952-B Stabilizer 12. #7406782 13. #7005909 left side) Panel Doors Feet Kick Plate Power Distribution Approximate Size-22” Approximate height-150 e Voltage-115 Panel (ac ?rrd dc, mounted wide, 39” deep (including Ibs. (without stabilizer feet), on upper 711/” high computer) V 60 Hz (for fans) 230 Y 50 Hz (for fans) PDP-11 POWER SUPPLY SUBSYSTEM H728-This Power supply is used in the Basic and Extension Mounting boxes and supplies power to all devices in.
UNIBUS MODULE (M920)-The M920 is a double module which connects the Unibus from one System Unit to the next within a Mounting Box. The A single M920 printed circuit cards are separated ‘by 1” for this-purpose. will carry all 56 Unibus signals .and 14 grounds. UNIBUS CABLE (BCllA)-The BCllA is a 120~conductor flexprint cable used to connect System Units in .different mounting boxes or a peripheral device which is removed from the mounting boxes.
. INSTALLATION .PROCEDlJRE The PDP-11 is crated for shipment to the customer site to prevent Installation is provided by DEC personnel at the customers site. Computer customers may send persorinel to instruction courses operation, programming, and maintenance conducted regularly Massachusetts, Palo Alto, California, and Reading, England. 83 damage.
The PDP-11 has adopted a moddlar packaging custom configuring of systems, easy expansion .. 84 approach to allow and easy servicing.
CHAPTER 11 PAPER TAPE SiFTWARE PAPER TAPE SOFTWARE SYSTEM (PTS) SYSTEM‘ ’ PTS is a compatible group of software packages designed to aid development of PDP-11 application programs. A brief description of each item with its major features is offered below with detailed programming information available in corresponding software user’s manuals.
Debugging operations alternate between commands to ODT and the running of the program to be debugged. Breakpoints are set in the user’s program by ODT commands, and a command to run starts execution of the program. When a breakpoint is encountered, the program run is suspended, and the progress of its execution can be monitored and altered. This is accomplished by using commands to open memory locations of interest, as well as special registers.
CHAPTER 12 1. ’ THE OPERATOR’S CONSOiE , ‘The PDP-11 Operator’s Console has been configured to achieve convenient control of the system. Through switches and keys on the console, programs or information can be manually inserted or modified. Also.indioator lamps on the console face display the status of the machine, the contents of t’he Bus Address Register and the data at the output of the data paths. _ The consoie is shown in Figure 12-1.
3. Bus-indicates that a peripheral is controlling the bus. It is lit when BBSY (Bus Busy) is asserted, unless the processor (which includes the Console) is asserting BBSY. 4. Run-indicates that the processor is running. It monitors the cdntrol flip-flop for the internal clock. 5. Source&ndicates that the central processor is. obtaining source data except from an internal register. 6. Destination-indicates that the central processor is obtaining des tination data (except from an internal register). 7.
When the system is running a program, the LOAD ADDR, EXAM, and DEPOSIT functions are disabled to prevent disrupting the,program. When the machine is to be halted, the ENABLE/HALT switch is thrown to the halt position. The machine will halt either at the end of the current instruction, or at the end of the current bus cycle, depending upon the position of the S/ INST-S/CYCLE switch. -OPERATING THE CONTROL SWlTCHES When the PDP-11 has been halted, it is possible to examine and update bus locations.
other lights; (Fetch, Execute, Source, Destination; the.Address lights, and the Address and Data registers) will be flickering. If the run light is on, and none ofthe other indicators are flickering, the system could. be executing a “wait” instruction which waits for an interrupt. While in the halt mode;if the operator wishes to do a siqgle instruction, he places the S/INST-S/CYCLE switch in the S/lNST position and depresses CONT.
APPENDIX A-PDFIi INSTRUCTION instruction Operation Mnemonic DOUBLE OPERAND GROUP: OPR scr;dst MOV(B) MOVe (Byte) (src) + (dst) CoMPare (Byte) Cm) - (dst) Blt Test (Byte) (src) A (dst) Blt Clear (Byte) - (src) A (dst) + (dst) Blt Set (Byte) (src) v (dst) + (dst) ADD ’ suBtra(@ + (dst) -, (dst) CMP(B) / BIT(B) BIG(B) BIS(B) ADD SUB ’ CONDITIONAL BR * BNE BEQ BGE BLT BGT BLE BPL BMI BHI BLOS BVC BVS , BCC (or BHIS) BCS (or BLO) (dst)‘- BRANCHES: REPERTOIRE OP Code Codes ZNCV .lSSDD / d-0 2.
SUBROUTINE 1JSR CALL: JSR reg,dst Jump to SubRoutine (dstb (tmp), 0%) J (PC> + (w3), Ww) + (PC) SUBROUTINE RETURN: RTS reg RTS ReTurn from Subroutine (w) + PC. t (w3) 004RDD - 4.2 00020R - 3.5 .050DD 1000 2.3 400 2.
RTI IOT RESET EMT TRAP - ReTurn from Interrupt 000002 4 d / / t Pa f (W Input/Output Trap 000004 d/v’/ (PSI 4 s (PC) 4, (20) + (PC), (22) + (PS) RESET 000005 an INIT oulse;s issued bv the CP EMulator Trap’ 104400--1104377 (PS) 4, (PC) 4, (30) + (PC), (32) + (PS)’ TRAP 104400-104777 4 PSI 4, (PC) 4 r (34) + (PC), (36) + (PSI 4.8 8.9 20 ms. NOTATION: 1. for order codes word/byte bit, set for byte (+lOOOOO) field, . SS-source DD-destination field XX-offset (8 bit) 2.
/ 94
APPENDIX R-ADDRESSING SUhMlARY ADDRESSING. ‘MODES. S,C or’ GENERAL REGISTER ADDRESSING Description Mode 0 ’ register 1 registerdeferred 2 auto increment auto increment deferred auto decrement auto decrementdeferred indexed indexed deferred 5 6 7 dst SymboJii Timing src 00’ $ R or (R) CR) + @ (RI + - CR) @ - 09 X CR) @ X (RI or @ CR) 1.5 1.5 2.7 1.5 2.7 2.7 3.9 (ws) dst 00 1.4 1.4 2.6 1.4 2.6 2.6 3.8 PC REGISTER ADDRESSING Timing f .
SUBROUTlNE CALL: JSR r*g.dsl SUBROUTINE RETURN; RTS rr9 0 , 15 0 I, 0 I I t 2 I I I 0 II 1 r*g II 3 2 0 . SINGLE OPERAND GROUP: OP OPR drt COOE I 6 15 CONDITION 0 CODE I I s, 0 OPERATORS: 0 1 I 15 0“ I 1 2 I I 4SNZVC 5432t . .
APPENDIX C-ADDRESS 0 4 USER DEVfCE INTERRUPT VECTOR BUS ERROR, ILLEGAL INSTRUCTION, STACK VECTOR RESERVED INSTRUCTIONS TRAP VECTOR CODE 000003 AND TRACE TRAP VECTOR IOT INSTUCTION TRAP VECTOR POWER FAIL INTERRUPT VECTOR .EMT INSTRUCTION TRAP VECTOR TRAP INSTUCTION TRAP VECTOR 10 14 i: 30 34 40 44 50, 54 z 70 74 . . . . . . 400 . . . .
177560 TELElYP;- KEYBOARD REGISTER -’ AND PUNCH DEVCE STATUS AND EUFFER . . . * 177576 17-7600 . 177677 177700 . . 1777;6 RESERVEP GENERAL CENTRAL FOR EXPANSION REGISTERS RO - OF PROCESSOR R7 PROCESSOR STATUS REGISTER (PS) .
. APPENDIX l+UNlBUS OPERATIONS There are ‘six bus operations: four to effect data transfers, on9 to transfer bus control, and one to effect a program interrupt. This appendix describes the signal interaction on the Unibus to perform these six operations.
l 5. Master sees SSYN and waits 75 nanoseconds, minimum (data deskewing + internal gating deskewing). data, drops MSYN, and waits 75 nanoseconds (des6. Master.strobes kew address). 7. Masfer drops A and C and waits for SSYN to fall. 8. Slave sees MSYN fall and drops SSYN and D lines. 9. Master sees SSYN fall, signaling-end of bus operation. NOTES: 1. Step 1 of the DATI P. ‘2. Step 2 of the DATIP.
\ NOTES: 1. Step 1 of the next-data transfer-may begin at step 5 of the current DATO or DATOB. 2. Step .2 of the next data transfer may begin at step 7 of the current DATO or DATOB. \ PTR-PRIORITY TRANSFER This bus operation is used to pass control of the bus from another. The steps which fbllow are performed simultaneously transfers: one master to with the data 0. Current master device always has BBSY asserted. device asserts its assigned BR line. 1. Requesting determines which BR is highest, and 2.
INTR-lNTerRupt This bus operation is initiated by a master immediately after receiving bus control to effect a program interrupt in the processor. It proceeds as follows: 0. Device has become bus master via PTR and BBSY is as&ted. Master puts interrupt vector address on D and asserts INTR. :: Processor sees INTR and waits 75 nanoseconds (deskewdata). Processor strobes data and asserts SSYN. :: Master sees SSYN, drops INTR, -D, and BBSY. The master has now relinquised bus control directly to the processor.
pitig BBSY); If control is given up actively, only NPR~requests will‘be honored during the interrupt sequence of.updating the PC and PS. If control is given up passively, control may pass either to +he processor to fetch the next instruction or to an NPR requesting device.
’ I c The PDP-11provides Direct Device Addressing. All memory-and devices on the Unibus are directly addressable and may be op erated upon by all computer instructions. Direct device to device transfers are possible. , .
