Technical information

Performance
Response time
Hysteresis
Characteristics
Clock output
Signal
Output pins
Function
Duration
Line driver
Maximum source current
Maximum sink current
Schmitt-Trigger 1 output
Signal
Output pins
Function
Other characteristics
Schmitt-Trigger 2 output
Signal
Output pin
Function
Other characteristics
Configuration Information
Power requirements
Power consumption
Bus loads
Depends on input waveform and amplitude; for
TTL logic levels, typically
600 nanoseconds
Approximately 0.5
V, positive and negative
Single-ended input with lOO-Kn impedance to
ground
CLK OV L (clock overflow, asserted low)
J1 pin 5 and CLK OVFL tab
Time base selection from an internal
crystal-controlled frequency, an input at ST1, or a
line frequency
at BEVNT bus line
Approximately 500 nanoseconds
TTL-compatible, open collector
circuit with a
470-D pull-up resistor to +5 V
5 mA when output is high (~2.4 V), measuring
from source through load to ground
8 mA when output is low (~0.8 V), measuring from
external source voltage through load to output
ST1 OUT L (asserted low)
J1 pin 2 and ST1 OUT tab
External time base input or counter of external
events. Input frequency is a function of the input
signal.
Same as clock output
ST2 OUT L (asserted low)
J1 pin 4
Starts counter, sets ST2 flag, and generates an
interrupt (if enabled); causes buffer preset register
(BPR) to be loaded from counter.
Same as clock output
+5 Vdc, 2.2 A (typical)
+12
Vdc, 0.013 A (typical)
11.156
W
1.0 ac
0.3 dc
Option Specifications 2-59