Specifications

Figure D–3: CPU Bus
A41 A42 A04 A35 BO5 BO6 BO7 B28 BO3 BO8 BO9 B50 B55 B54 B49 B53 B48 B52 B47 B36 B35 B36 B37 B40 B39 B42 B41 A56
A41 A42 A04 A35 BO5 BO6 BO7 B28 BO3 BO8 BO9 B50 B55 B54 B49 B53 B48 B52 B47 B36 B35 B36 B37 B40 B39 B42 B41
SOD
SID
A788 (TSM)
PSCSO (SWMCS)
CPURD
CPUWR
CPUIO/M
CPUADR11 CPUADR10
CPUADR9 CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 CPUADR0
CPUAD0 CPUAD1 CPUAD2 CPUAD3 CPUAD4 CPUAD5 CPUAD6 CPUAD7
RESET
SOD SID A788 (TSM) PSCSO (SWMCS) CPURD CPUWR CPUIO/M CPUADR11 CPUADR10 CPUADR9 CPUADR8 CPUADR7 CPUADR6 CPUADR5 CPUADR4 CPUADR3 CPUADR2 CPUADR1 CPUADR0 CPUAD0 CPUAD1 CPUAD2 CPUAD3 CPUAD4 CPUAD5 CPUAD6 CPUAD7
SMSM
(PIGGYBACK
ON SMSM)
SMSI
SMIM
SMIH
RESET CPUAD7 CPUAD6 CPUAD5 CPUAD4 CPUAD3 CPUAD2 CPUAD1 CPUAD0 CPUADR0 CPUADR1 CPUADR2 CPUADR3 CPUADR4 CPUADR5 CPUADR6 CPUADR7 CPUADR8 CPUADR9 CPUI0/M CPUWR CPURD
A56 B41 B42 B39 B40 B37 B38 B35 B36 B47 B52 B48 B53 B49 B54 B55 B50 B09 B08 B07 B06 B05
SMMB
A09
A10
A12
B12
A22
A25
A23
B11
A18
A07
A17
A19
B04
B17
A56
A09
A10
A12
B12
A22
A25
A23
B11
A18
A07
A17
A19
B04
B17
A6CF
A747
A7CF
ALE 1
BEGIN
DIBCS
NFP
RDY3
STOP3
ALE 2
IR5
IR4
RDY 1
OSC
RESET
A6CF
A747
A7CF
ALE 1
BEGIN
DIBCS
NFP
RDY3
STOP3
ALE 2
IR5
IR4
RDY 1
OSC
See also
Figs. D2, D4,
See also
Figs. D4, D5
See also
Figs. D4, D5
See also
Figs. D2, D4, D5
RE_UK01417M_89
D–4 LG31 INTERCONNECTION DIAGRAMS