Specifications

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Central Processor
PDP-ll compatibility mode
Time bases
110 bus interface
Termination
Specification
Emulated in software
Time-of-year clock: 1 (battery backed up)
Interval timer: 1
(10 milliseconds)
Programmable timers: 2
One Q22-bus interface with 8192
entry "scatter gather" map registers
240n
Memory Management and Control
Page size
Virtual address space
Physical memory space
Number of memory modules
Performance
Instruction prefetch buffer size
Cache
Size
Speed
Associativity
Translation buffer
Size
Associativity
Q22-bus address
translation map cache
Size
Associativity
110 bus buffer size
Input
Output
512 bytes
4 gigabytes
28 Mbytes
3 maximum
Specification
12 bytes
1 Kbyte
100 nanoseconds
2-way
set
28-entry
Fully associative
16-entry
Fully associative
32 bytes
4 bytes
Base System Specifications 1-11