Technical data

Overview
1–2
DIGITAL HiNote Ultra 2000 Service Guide
Chip Set
The PicoPower Vesuvius chip set is used to implement the core functions of the
system.
•
The V1 and V2 chips provide the core system functions.
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Support for all Intel Pentium processors.
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Support for write-through secondary (L2) cache.
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Eight level write post buffer to DRAM (2-1-1-1 writes @ 66MHz).
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32/64-bit DRAM interface.
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DRAM timing, bus width, and type programmable DRAM interface on a bank by
bank basis.
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PCI bus arbiter.
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Hot docking support for PCI/ISA docks.
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Advanced Power Management features.
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The V2 chip provides the PCI bus interface and the interface between the V1 and
memory.
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The V3 chip provides the PCI to ISA bridge interface.
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PCI-to-ISA bridge.
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Full ISA bus support in positive decode and subtractive mode.
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Distributed DMA protocol support.
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Serialized IRQ protocol support.
Memory
The system comes with 16MB of on-board EDO DRAM for system memory and 512KB of L2
cache memory.
System memory can be upgraded to a total of 144MB. The upgrade is performed by installing
8MB, 16MB, 32MB or 64MB EDO SO-DIMMs. There are two slots for additional memory.
Memory can be upgraded one module at a time. Either slot can be populated first.
BIOS
The system has an Intel 28F002BX-T 2MB Boot block Flash ROM for system BIOS. BIOS
provides support for the following:
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Suspend to RAM.
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Full APM 1.2 supported.
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Password protection (System and Docking options).
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Auto-configured with docking options.
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Windows 95 ready with PnP.
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Various hot-keys for system control.