Specifications

Memory Subsystem 4-1
Chapter 4
Memory Subsystem
The memory subsystem consists of hierarchically accessed levels that re-
side in different locations in the system. The memory hierarchy consists of
three main parts:
• Internal Caches - These caches reside on the DECchip 21164.
• Backup Cache - This cache is external to the DECchip 21164 and re-
sides on the CPU module.
• Main Memory - Consists of one or more memory modules.
4.1 Internal Cache
The DECchip 21164 contains three on-chip caches:
• Instruction cache
• Data cache
• Second-level cache
4.1.1 Instruction Cache
The instruction cache (I-cache) is a virtually addressed direct-mapped
cache. I-cache blocks contain 32 bytes of instruction stream data, associ-
ated predecode data, the corresponding tag, a 7-bit ASN (Address Space
Number) field (MAX_ASN=127), a 1-bit ASM (Address Space Match) field,
and a 1-bit PALcode instruction per block. The virtual instruction cache is
kept coherent with memory through the IMB PAL call, as specified in the
Alpha SRM.
4.1.2 Data Cache
The data cache (D-cache) is a dual-ported cache implemented as two 8-
Kbyte banks. It is a write through, read allocate direct-mapped physically
addressed cache with 32-byte blocks. The two cache banks contain identi-
cal data. The DECchip 21164 maintains the coherency of the D-cache and
keeps it a subset of the S-cache (second-level cache).
A load that misses the D-cache results in a D-cache fill. The two banks are
filled simultaneously with the same data.