Specifications

3-18 CPU Module
3.5.2.3 No Acknowledge Errors
Whenever a commander node expects but does not receive an acknowledg-
ment of its address transmission as an assertion of TLSB_CMD_ACK, it
sets an error bit in its TLBER register. For memory space accesses that
are not acknowledged, <FNAE> is set: for CSR accesses, <NAE> is set.
The exception to this rule is a CSR write to I/O mailbox registers; no ac-
knowledgment is not regarded as an error. No acknowledgment of memory
space addresses is regarded as a fatal error and causes TLSB_FAULT to
be asserted. No acknowledgment of CSR reads causes a dummy fill to be
performed with the FILL_ERROR signal set to the DECchip 21164, and in-
ititates the DECchip 21164 error handler.
I/O module generated broadcast writes to the counter decrement registers
for Memory Channel and window space accesses are not acknowledged.
These writes should not cause errors.
All nodes monitor TLSB_CMD_ACK. A data bus transaction follows every
acknowledged command.
3.5.2.4 Unexpected Acknowledge Error
Every node monitors TLSB_CMD_ACK every cycle and sets <UACKE> if
it detects an unexpected assertion of TLSB_CMD_ACK. This error results
in the assertion of TLSB_FAULT.
A node expects TLSB_CMD_ACK only in a valid address bus sequence
with no errors. TLSB_CMD_ACK is not expected:
• When not in a valid address bus sequence
• In response to a no-op command
3.5.2.5 Memory Mapping Register Error
A commander node translates a memory address to a bank number before
issuing every command. This translation is performed by examining the
contents of the TLMMRn registers in the node. The <MMRE> error bit is
set if no bank number can be determined from the memory address.
This error is not broadcast. A machine check is generated by the ADG. If
the address is issued on the bus, the command is a no-op.
3.5.3 Data Bus Errors
Data bus errors are either ECC-detected errors on data transfers or control
errors on the data bus. In addition, all drivers of the TLSB check the data
received from the bus against the expected data driven on the bus.
The TLSB_D<255:0> and TLSB_ECC<31:0> signals are sliced into four
parts, each containing 64 bits of data and 8 bits of ECC. Error detection on
these signals is handled independently in each slice, setting error bits in a
corresponding TLESRn register. The contents of the four TLESRn regis-
ters are summarized in the TLBER register. The most significant error
type can be determined from the TLBER register.