Specifications

3-12 CPU Module
Table 3-5 PCI Address Bit Descriptions
3.4.4.1 Sparse Space Reads and Writes
In PCI sparse space, 128 bytes of address are mapped to one longword of
data. Data is accessible as bytes, words, tribytes, longwords, or
quadwords.
Bits <4:3> of the address do not appear on the DECchip 21164 address
bus. They must be inferred from the state of the INT4 mask bits. For
sparse reads the CPU module generates and transmits the appropriate
bits <4:3> on the TLSB_ADR bus. For writes, the entire 32-byte block of
Name Bit(s) Function
IO_SPACE
IOP_SEL
HOSE
PCI_SPACE_TYP
ADDRESS
ADDRESS
<39>
<38:36>
<35:34>
<33:32>
<31:05>
<4:3>
DECchip 21164 I/O space if set to 1.
Selects address space as follows:
Selects hose number on that module
Selects PCI address space type as follows:
PCI address.
PCI address. When bits <33:32> = 01 or 10, the length
decode is as follows:
Otherwise bits <4:3> are part of the longword address.
Bits <38:36> Selected Space
000
001
010
011
100
Node 4
Node 5
Node 6
Node 7
Node 8
Bits <33:32> PCI Address Space Selected
00
01
10
11
Dense memory address space
Sparse I/O space address
Sparse I/O space address
Configuration space address
Bits <4:3> Length
00
01
10
11
Byte
Word
Tribyte
Longword or quadword