Specifications

CPU Module 3-7
from cache or the TLSB as shown in Table 3-2. Bit <4> specifies which
16-byte portion of the 32-byte subblock is returned first from the DIGA or
cache. Bits <3:0> specify the byte being accessed.
Table 3-2 TLSB Wrapping
Table 3-3 CPU Module Wrapping
3.3.1 Memory Space
Bit <39> differentiates between cacheable and noncacheable address
spaces. If bit <39> is zero, the access is to memory space; if it is one, the
access is to I/O space.
TLSB_ADR<5> Data Return Order
0
1
Data returned in order
Data Cycle 0 -> Hexword 0
Data Cycle 1 -> Hexword 1
Data returned out of order
Data Cycle 0 -> Hexword 1
Data Cycle 1 -> Hexword 0
DECchip 21164
ADDR<5:4> Data Return Order from Cache
00
01
10
11
Fill Cycle 0 -> Octaword 0
Fill Cycle 1 -> Octaword 1
Fill Cycle 2 -> Octaword 2
Fill Cycle 3 -> Octaword 3
Fill Cycle 0 -> Octaword 1
Fill Cycle 1 -> Octaword 0
Fill Cycle 2 -> Octaword 3
Fill Cycle 3 -> Octaword 2
Fill Cycle 0 -> Octaword 2
Fill Cycle 1 -> Octaword 3
Fill Cycle 2 -> Octaword 0
Fill Cycle 3 -> Octaword 1
Fill Cycle 0 -> Octaword 3
Fill Cycle 1 -> Octaword 2
Fill Cycle 2 -> Octaword 1
Fill Cycle 3 -> Octaword 0