Specifications
TLSB Bus 2-39
Table 2-10 Address Bus Error Summary
2.4.4 Data Bus Errors
Data bus errors are either ECC-detected errors or control errors. In addi-
tion, all drivers of the TLSB check the data received from the bus against
the expected data driven on the bus.
The TLSB_D<255:0>, TLSB_ECC<31:0>, and TLSB_DATA_VALID<3:0>
signals are sliced into four parts, each containing 64 bits of data, 8 bits of
ECC, and one valid bit. Error detection on these signals is handled inde-
pendently in each slice, setting error bits in a corresponding TLESRn reg-
ister as shown in Table 2-11.
Table 2-11 Signals Covered by TLESRn Registers
The contents of the four TLESRn registers is summarized in the TLBER
register. The most significant error type can be determined from the TL-
BER register. Broadcasting of the error and latching the TLFADRn regis-
ters are determined from the TLBER register.
Error Description Who Detects Signal
ATCE
APE
BBE
LKTO
NAE
FNAE
RTCE
ACKTCE
MMRE
UACKE
ABTCE
REQDE
Address Transmit Check Error
Address Parity Error
Bank Busy Violation Error
Bank Lock Timeout
No Acknowledge to CSR Access
No Acknowledge to Memory Access
Request Transmit Check Error
Acknowledge Transmit Check Error
Memory Mapping Register Error
Unexpected Acknowledge
Address Bus Transmit Check Error
Request Deassertion Error
Commander
All
All
1
Memory
Commander
Commander
Commander
Slave
Commander
All
All
Commander
TLSB_FAULT
TLSB_FAULT
TLSB_FAULT
None
None
TLSB_FAULT
TLSB_FAULT
TLSB_FAULT
None
TLSB_FAULT
TLSB_FAULT
TLSB_FAULT
1
All nodes set BBE for a CSR busy violation; only memory nodes set BBE for memory bank busy violations.
Register TLSB_D TLSB_ECC TLSB_DATA_VALID
TLESR0
TLESR1
TLESR2
TLESR3
<63:0>
<127:64>
<191:128>
<255:192>
<7:0>
<15:8>
<23:16>
<31:24>
<0>
<1>
<2>
<3>