Specifications

2-30 TLSB Bus
2.3.2 TLSB Mailboxes
CSRs that exist on external I/O buses connected to an I/O port (or another
I/O module implementing mailbox register access) are accessed through
mailbox structures that exist in main memory. Read requests are posted
in mailboxes, and data and status are returned in the mailbox. Mailboxes
are allocated and managed by operating system software (successive op-
erations must not overwrite data that is still in use).
The I/O module services mailbox requests through a mailbox pointer CSR
(TLMBPR) located in the I/O module’s node space. When the CPU writes
this CSR, it must assert its virtual ID on TLSB_BANK_NUM<3:0>. The
I/O module provides a separate register for each CPU.
Software sees a single TLMBPR address with the CPU virtual ID selecting
one of the 16 registers. If all 16 TLMBPRs are implemented, one register
is accessed for each address. If the eight optional registers are not imple-
mented, the I/O module must ignore TLSB_BANK_NUM<3> and access
one of the eight implemented registers.
Implementation of eight TLMBPRs implies that eight CPUs can uniquely
access remote CSRs. This implementation is sufficient to handle up to four
CPU nodes on the TLSB bus where each CPU node may be a dual CPU.
The way I/O modules map the 16 virtual IDs to the eight TLMBPRs allows
flexibility in CPU virtual ID assignments, that is, virtual IDs 8–15 can be
used provided each CPU maps to a unique TLMBPR. With more than
eight CPUs, registers are shared, with up to two CPUs accessing one regis-
ter.
If a TLMBPR is in use when it is written to, the I/O module does not ac-
knowledge it (TLSB_CMD_ACK is not asserted). Processors use the lack
of TLSB_CMD_ACK assertion on writes to the TLMBPR to indicate a busy
status. The write must be reissued at a later point. The mailbox pointer
CSR is described in Chapter 7.
TLMBPR points to a naturally aligned 64-byte data structure in memory
that is constructed by software as shown in Figure 2-6.
Figure 2-6 Mailbox Data Structure
63 48 47 40 39 32 31 012
MBZ MBZ CMD
BXB-0174 C-94
RBADR <63:0>
WDATA <63:0>
UNPREDICTABLE
RDATA <63:0>
STATUS
E
R
R
D
O
N
UNPREDICTABLE
UNPREDICTABLE
MASK
QW 0
QW 1
QW 2
QW 3
QW 4
QW 5
QW 6
QW 7
56 55
HOSE
BW
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