Specifications

TLSB Bus 2-29
Table 2-8 TLSB CSR Address Mapping
Address Name Mnemonic
Modules That
Implement
BB+000
BB+040
BB+080
BB+0C0
BB+200
BB+240
BB+280
BB+2C0
BB+300
BB+340
BB+380
BB+3C0
BB+600
BB+640
BB+680
BB+6C0
BB+700
BB+740
BB+A00
BB+A40
BB+A80
BB+AC0
BB+B00
BB+C00
1
BSB+000
BSB+040
BSB+100
BSB+140
BSB+180
BSB+1C0
BSB+200
BSB+400
BSB+440
BSB+480
BSB+4C0
BSB+500
BSB+600
BSB+640
BSB+800
BSB+840
BSB+1880
Device Register
Bus Error Register
Configuration Register
Virtual ID Register
Memory Mapping Register
Memory Mapping Register
Memory Mapping Register
Memory Mapping Register
Memory Mapping Register
Memory Mapping Register
Memory Mapping Register
Memory Mapping Register
TLSB Failing Address Register 0
TLSB Failing Address Register 1
TLSB Error Syndrome Register 0
TLSB Error Syndrome Register 1
TLSB Error Syndrome Register 2
TLSB Error Syndrome Register 3
Interrupt Level0 IDENT Register
Interrupt Level1 IDENT Register
Interrupt Level2 IDENT Register
Interrupt Level3 IDENT Register
CPU Interrupt Mask Register
Mailbox Pointer Register
Reserved for private transactions
IP Interrupt Register
I/O Interrupt Register
I/O Interrupt Register
I/O Interrupt Register
I/O Interrupt Register
I/O Interrupt Register
Window Space Decr Queue Counter Reg 4
Window Space Decr Queue Counter Reg 5
Window Space Decr Queue Counter Reg 6
Window Space Decr Queue Counter Reg 7
Window Space Decr Queue Counter Reg 8
Reflective Mem Decr Queue Counter Reg X
Reflective Mem Decr Queue Counter Reg 8
CSR Read Data Return Data Register
CSR Read Data Return Error Register
Memory Control Register
TLDEV
TLBER
TLCNR
TLVID
TLMMR0
TLMMR1
TLMMR2
TLMMR3
TLMMR4
TLMMR5
TLMMR6
TLMMR7
TLFADR0
TLFADR1
TLESR0
TLESR1
TLESR2
TLESR3
TLILID0
TLILID1
TLILID2
TLILID3
TLCPUMASK
TLMBPR
TLPRIVATE
TLIPINTR
TLIOINTR4
TLIOINTR5
TLIOINTR6
TLIOINTR7
TLIOINTR8
TLWSDQR4
TLWSDQR5
TLWSDQR6
TLWSDQR7
TLWSDQR8
TLRMDQRX
TLRMDQR8
TLRDRD
TLRDRE
TLMCR
CPU, Memory, I/O
CPU, Memory, I/O
CPU, Memory, I/O
CPU, Memory
CPU, I/O
CPU, I/O
CPU, I/O
CPU, I/O
CPU, I/O
CPU, I/O
CPU, I/O
CPU, I/O
CPU, Memory, I/O
CPU, Memory, I/O
CPU, Memory, I/O
CPU, Memory, I/O
CPU, Memory, I/O
CPU, Memory, I/O
I/O
I/O
I/O
I/O
I/O
I/O
None
2
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU, I/O
CPU, I/O
CPU
CPU
Memory
1
Virtual CPU ID asserted on TLSB_BANK_NUM<3:0> to select one of 16 registers.
2
Data not to be recorded by another node.