Specifications

TLSB Bus 2-27
Figure 2-5 TLSB CSR Space Map
All TLSB node CSRs are 32 bits wide, except the TLMBPR and TLRDRD
registers, which are wider. Data is always right justified on the data bus,
with bit <0> of the register transmitted on TLSB_D<0> in the first data
cycle. All bits above the defined register width must be considered Unpre-
dictable.
Node private space is reserved for local use on each module. Nodes may
allocate additional reserved address space for local use. References to re-
served addresses are serviced by resources local to a module.
Broadcast space is for write-only registers that are written in all nodes by
a single bus transaction. Broadcast space is used to implement vectored
and interprocessor interrupts.
Broadcast space register 0 (TLPRIVATE) is reserved for private transac-
tions. Data written to this register is ignored by other nodes. Any data
values may be written.
Table 2-7 gives the TLSB node base addresses (BB) and shows what kind
of module can be in the slot.
Byte Address
F0 0000 0000

FF 87FF FFC0
FF 8800 0000

FF 883F FFC0
FF 8840 0000

FF 887F FFC0

. . . 

FF 8A00 0000

FF 8A3F FFC0
FF 8A40 0000

FF 8DFF FFC0
FF 8E00 0000

FF 8E3F FFC0
FF 8E40 0000

FF FFFF FFC0


Reserved
Node 0 CSRs: 64K CSR Locations
Reserved
Broadcast Space: 64K CSR Locations
Reserved
BXB-0780A-94
Node 1 CSRs: 64K CSR Locations
Node 8 CSRs: 64K CSR Locations
. . .