Specifications

2-16 TLSB Bus
in subsequent CSR accesses, and it is not ready to source or accept data, it
can delay asserting TLSB_SEND_DATA, or it can assert TLSB_HOLD on
the bus.
2.2.4.15 Command Acknowledge
When a device asserts an address, bank number, and a valid data transfer
command on the bus, the targeted device responds two cycles later by as-
serting TLSB_CMD_ACK. This indicates that the command has been re-
ceived and that the targeted address is valid. In the case of CSR broadcast
space writes, where there may be multiple targeted devices, the bus com-
mander asserts TLSB_CMD_ACK.
If an acknowledge is not received, the data bus is not cycled for this com-
mand (that is, treated as a no-op). Two cases exist where no acknowledge
is not an error condition: (1) An I/O port does not respond to a CSR access
to a mailbox pointer register. This indicates that the mailbox pointer reg-
ister is full and that the access should be retried later; (2) A broadcast
space register write, where the act of writing an address is meaningful, but
no data needs to be transmitted.
2.2.4.16 Arbitration Suppress
The commander module asserts TLSB_ARB_SUP to limit the number of
outstanding transactions on the bus to 16. This signal must be asserted in
the cycle following an arbitration cycle, that is in the cycle in which a com-
mand, address, and bank number are driven. TLSB_ARB_SUP is asserted
for one cycle, then deasserted for one cycle. This two-cycle sequence is re-
peated until arbitration can be permitted again. Multiple nodes may as-
sert TLSB_ARB_SUP the first time and the same or fewer nodes may as-
sert it every two cycles thereafter until finally it is not asserted. The cycle
in which it is not asserted is the next request cycle if any device request
signals are asserted at that time; otherwise it is an idle cycle.
Nodes must disregard the value of TLSB_ARB_SUP received during the
second of each two-cycle sequence, as it is Unpredictable. An assertion of
TLSB_ARB_SUP should be converted internally to look like a two-cycle as-
sertion and ignore the value received in the second cycle. This entire se-
quence repeats every two cycles until it is received deasserted.
Modules may assert requests while TLSB_ARB_SUP is asserted, but no
arbitration is allowed. Priority of devices does not change while
TLSB_ARB_SUP is inhibiting arbitration cycles. Arbitration, when it re-
sumes, follows the normal rules for priority levels and look-back-two.
TLSB_ARB_SUP may also be asserted in response to TLSB_FAULT.
2.2.5 Address Bus Cycles
A TLSB address bus cycle is the time occupied by two cycles of the TLSB
clocks. During the first clock cycle the address, bank, and command bus
signals are driven by the commanding node. The second clock cycle is used
for a dead cycle. This leads to a simpler electrical interface design and the
lowest achievable clock cycle time. There are two types of legal address
bus cycles:
• Data transfer command cycles