Specifications

2-14 TLSB Bus
in a request cycle, that CPU must take part in the following arbitration cy-
cle even if the bus is no longer required. If the device wins the bus, it as-
serts a no-op on the bus command lines.
I/O devices in the dedicated I/O port node cannot use early arbitration.
2.2.4.9 False Arbitration Effect on Priority
Relative bus priorities are only updated when a data transfer command is
asserted on the bus. If a device false arbitrates and drives a no-op on the
bus, the bus priorities are not updated.
2.2.4.10 Look-Back-Two
To avoid the possibility of a low-priority device being held off the bus by
high-priority devices false arbitrating, a mechanism is provided that as-
signs a higher priority to requests that have been continuously asserted for
more than two cycles. This is referred to as the "look-back-two" mecha-
nism.
A request line continuously asserted for more than two cycles must be a
real request (that is, not early, not false). Since bank decode and cache
miss are resolved after two cycles, real requests must be serviced before
newer, potentially false requests. When one or more requests have been
asserted continuously for more than two cycles, these requests have
higher priority than newer requests, and the arbiters consider only re-
quests falling into that category. If the new requests are kept asserted for
longer than two cycles, they are included in the arbitration. The effects of
early arbitration, therefore, are noticed only on buses that are not continu-
ously busy. Busy buses tend to have a queue of outstanding requests wait-
ing to get the bus granted. Requests due to early arbitration are at a lower
priority and are not granted the bus.
If two devices request the bus at the same time, the higher priority device
wins the bus. If the losing device keeps its request line asserted, this is
understood to be a real request, and the device is assigned a higher prior-
ity than any newer (potentially false) requests. Note that only a device
continuously asserting its request line for more than two bus cycles is
treated in this manner. Devices must deassert their request line for at
least one cycle between consecutive requests.
NOTE: The I/O port request line TLSB_REQ8_HIGH always has the highest prior-
ity, even in the look-back-two situation.
2.2.4.11 Bank Available Transition
A device can only arbitrate for a bank that is not currently in use. The
TLSB_BANK_AVL<15:0> signals are used to indicate the busy state of the
16 memory banks. TLSB_BANK_AVL lines will be assigned in the mem-
ory by the virtual ID loaded by console software at power-up or after sys-
tem reset. When a bank becomes free, the TLSB_BANK_AVL line associ-
ated with it is asserted. There is a window of time after the command is
asserted on the bus before the memory can respond by deasserting the
TLSB_BANK_AVL signal. Consequently, devices must monitor the bus to
determine when a bank becomes busy.