Specifications

2-12 TLSB Bus
2.2.4 Address Bus Arbitration
The TLSB bus has demultiplexed address and data buses. These buses op-
erate independently and are related only in as much as a valid command
on the address bus will result in a data transfer on the data bus at some
later time.
2.2.4.1 Initiating Transactions
To initiate a bus transaction, a module must request the bus and arbitrate
for access to the bus with other requesting modules. Only when it wins ar-
bitration can a device drive the command, address, and memory bank
number onto the bus. Only CPUs and I/O modules can initiate transac-
tions.
2.2.4.2 Distributed Arbitration
The TLSB uses a distributed arbitration scheme. Ten request lines
TLSB_REQ8_HIGH, TLSB_REQ8_LOW, and TLSB_REQ<7:0> are driven
by the CPU or I/O modules that wish to use the bus. All modules inde-
pendently monitor the request lines to determine whether a transaction
has been requested, and if so, which module wins the right to send a com-
mand cycle. Request lines are assigned to each node. Nodes 7–0 are as-
signed TLSB_REQ<7:0>, respectively. Node 8, the dedicated I/O port
node, is assigned TLSB_REQ8_HIGH and TLSB_REQ8_LOW. At power-
up, or following a reset sequence, the relative priority of each of the re-
quest lines TLSB_REQ<7:0> is initialized to the device’s node ID. Node 7
has the highest relative priority and node 0 the lowest.
2.2.4.3 Address Bus Transactions
CPU and I/O modules can only perform transfers to or from memory banks
that are not currently in use, plus one transfer to or from a CSR. The
maximum number of memory banks in a system is 16. Consequently, the
maximum number of outstanding transactions possible on the bus at one
time is 17. However, due to the size of the sequence number tagged to
each transaction, a limit of 16 outstanding transactions must be enforced.
All CPU and I/O modules are required to assert TLSB_ARB_SUP to pre-
vent arbitration for a 17th command. Individual modules may limit the
number of transactions on the bus to a lower number.
2.2.4.4 Module Transactions
There is no limit to the number of transactions that can be issued by one
module as long as each of the transactions meets the requirements of tar-
geting a nonbusy bank and of requesting the bus separately for each trans-
action.
2.2.4.5 Address Bus Priority
Each commander node keeps track of the relative priorities of the request
lines TLSB_REQ<7:0>. When a device wins the bus and issues a data
transfer command, it becomes the lowest priority device. Any device whose
priority is below that of the winning device has its priority incremented.