Specifications
iv
2.2.4.3 Address Bus Transactions ............................................................................. 2-12
2.2.4.4 Module Transactions...................................................................................... 2-12
2.2.4.5 Address Bus Priority...................................................................................... 2-12
2.2.4.6 Address Bus Request ..................................................................................... 2-13
2.2.4.7 Asserting Request .......................................................................................... 2-13
2.2.4.8 Early Arbitration ........................................................................................... 2-13
2.2.4.9 False Arbitration Effect on Priority .............................................................. 2-14
2.2.4.10 Look-Back-Two............................................................................................... 2-14
2.2.4.11 Bank Available Transition ............................................................................ 2-14
2.2.4.12 Bank Collision ................................................................................................ 2-15
2.2.4.13 Bank Lock and Unlock................................................................................... 2-15
2.2.4.14 CSR Bank Contention.................................................................................... 2-15
2.2.4.15 Command Acknowledge................................................................................. 2-16
2.2.4.16 Arbitration Suppress ..................................................................................... 2-16
2.2.5 Address Bus Cycles .............................................................................................. 2-16
2.2.6 Address Bus Commands ...................................................................................... 2-17
2.2.7 Data Bus Concepts ............................................................................................... 2-18
2.2.7.1 Data Bus Sequencing..................................................................................... 2-18
2.2.7.2 Hold................................................................................................................. 2-18
2.2.7.3 Back-to-Back Return Data ............................................................................ 2-19
2.2.7.4 Back-to-Back Return with HOLD ................................................................. 2-19
2.2.7.5 CSR Data Sequencing.................................................................................... 2-19
2.2.8 Data Bus Functions.............................................................................................. 2-19
2.2.8.1 Data Return Format ...................................................................................... 2-19
2.2.8.2 Sequence Numbers......................................................................................... 2-20
2.2.8.3 Sequence Number Errors .............................................................................. 2-20
2.2.8.4 Data Field....................................................................................................... 2-20
2.2.8.5 Data Wrapping............................................................................................... 2-20
2.2.8.6 ECC Coding .................................................................................................... 2-21
2.2.8.7 ECC Error Handling ...................................................................................... 2-22
2.2.8.8 TLSB_DATA_VALID ..................................................................................... 2-22
2.2.8.9 TLSB_SHARED ............................................................................................. 2-22
2.2.8.10 TLSB_DIRTY ................................................................................................. 2-23
2.2.8.11 TLSB_STATCHK ........................................................................................... 2-23
2.2.9 Miscellaneous Bus Signals................................................................................... 2-24
2.3 CSR Addressing .......................................................................................................... 2-25
2.3.1 CSR Address Space Regions ................................................................................ 2-26
2.3.2 TLSB Mailboxes.................................................................................................... 2-30
2.3.3 Window Space I/O................................................................................................. 2-32
2.3.3.1 CSR Write Transactions to Remote I/O Window Space............................... 2-32
2.3.3.2 CSR Read Transactions to Remote I/O Window Space................................ 2-32
2.4 TLSB Errors ................................................................................................................ 2-33
2.4.1 Error Categories ................................................................................................... 2-34
2.4.1.1 Hardware Recovered Soft Errors ................................................................. 2-34
2.4.1.2 Software Recovered Soft Errors .................................................................... 2-34
2.4.1.3 Hard Errors .................................................................................................... 2-34
2.4.1.4 System Fatal Errors....................................................................................... 2-34
2.4.2 Error Signals......................................................................................................... 2-35
2.4.3 Address Bus Errors .............................................................................................. 2-35
2.4.3.1 Transmit Check Errors.................................................................................. 2-35
2.4.3.2 Command Field Parity Errors....................................................................... 2-36
2.4.3.3 No Acknowledge Errors ................................................................................. 2-36
2.4.3.4 Unexpected Acknowledge .............................................................................. 2-37
2.4.3.5 Bank Lock Error............................................................................................. 2-37
2.4.3.6 Bank Available Violation Error..................................................................... 2-37
2.4.3.7 Memory Mapping Register Error .................................................................. 2-38