Specifications

8-6 Interrupts
TLIPINTR register and interrupts either (or both) of the CPUs as appro-
priate, based on their virtual node IDs. The interprocessor interrupt is
cleared by a write to TLINTRSUM<IP>.
8.3.5 Module-Level Interrupts
The CPU module uses the hardware interrupts provided as shown in Table
8-1. The handling of interrupts from I/O devices, the interval timer, and
UARTs is under both hardware and PALcode control.
Table 8-1 CPU Module Interrupts
Note that there are three sources of CPU interrupts at IPL 16 and two
sources of interrupts at IPL 14.
On receiving an IRQ<2> or an IRQ<0> interrupt, the CPU reads the TLIN-
TRSUM register. Bits <0> and <1> of the TLINTRSUM register are logi-
cally ORed together to drive IRQ0 into the DECchip 21164. Bits <4>, <6>,
and <7> of the TLINTRSUM register logically ORed together drive
IRQ<2> into the DECchip 21164. This register therefore provides a means
for determining the source of IPL14 and IPL16 interrupts to the processor.
I/O interrupts to a particular processor can be disabled using the TLCPU-
MASK registers and/or the TLINTRMASK register. Interprocessor inter-
rupts, UART interrupts, and interval timer interrupts can be disabled by
using the TLINTRMASK registers.
IPL Interrupt Condition DECchip Interrupt Pin
1F
1F
1F
17
16
16
16
15
14
14
Machine check
CTRL/P detection
Node Halt (TLCNR.HALT_x)
IPL 17 I/O port interrupts
Interval timer
Interprocessor interrupt
IPL 16 I/O port interrupts
IPL 15 I/O port interrupts
CPU console/power UARTs
IPL 14 I/O port interrupts
SYS_MCH_CHK_IRQ
MCH_HLT_IRQ
MCH_HLT_IRQ
IRQ3
IRQ2
IRQ2
IRQ2
IRQ1
IRQ0
IRQ0