Specifications

8-2 Interrupts
• At most, four interrupts at levels 0, 1, and 2 can be pending on the
TLSB bus (one per interrupt level 14, 15, and 16, respectively, per I/O
hose) per I/O node.
• However, up to five interrupts at level 3 can be pending on the TLSB
bus (one at interrupt level 17 per I/O hose and one internally gener-
ated I/O module error interrupt) per I/O node.
• When a CPU module performs a CSR read of a given TLILIDn regis-
ter, the I/O module considers the relevant interrupt to be serviced.
• Multiple CPUs can be targeted for a single interrupt at a given level.
This is specified by the contents of the TLCPUMASK register.
• If a CPU performs a TLSB CSR read of a given TLILIDn register for a
given interrupt level and the I/O module considers all the interrupts
posted at that level to be serviced, the I/O module returns a value of
zero as CSR read data (passive release).
8.1.2 CPU Interrupt Rules
Both AlphaServer 8200 and 8400 systems support up to three I/O modules.
Each I/O module can generate four interrupts at level 0, four at level 1,
four at level 2, and five at level 3. Thus, one I/O port can have 17 out-
standing interrupts. In a system with three I/O ports there can be up to 51
outstanding interrupts.
A CPU module services an interrupt by reading from the TLILIDn regis-
ter indexed with the physical node ID of the interrupting I/O device.
To store all outstanding interrupt requests, a CPU keeps a count of the
number of requests at each level and the physical node ID of the interrupt-
ing I/O device. CPUs can do this by keeping an outstanding interrupt
count (in the range 0–4 for levels 0, 1, and 2; 0–5 for level 3) for each level,
for each I/O device.
8.1.3 I/O Port Interrupt Operation
The following observations apply to the I/O port interrupt operation:
• An I/O adapter posts an interrupt at a given interrupt level.
• The I/O module assembles the interrupt vector in the queue for the
relevant interrupt level for a later read of the appropriate TLILIDn
register. The I/O module then issues a CSR write transaction over the
TLSB bus to one of five TLIOINTRn registers using the TLCPUMASK
register to specify which target CPUs are to receive the interrupt.
• During the CSR write transaction the I/O module asserts its node ID
on the four least significant address bits of the TLSB bus. These four
bits determine the specific TLIOINTRn register to be written as fol-
lows:
— Node ID 4 = TLIOINTR4 register
— Node ID 5 = TLIOINTR5 register
— Node ID 6 = TLIOINTR6 register
— Node ID 7 = TLIOINTR7 register
— Node ID 8 = TLIOINTR8 register