Specifications

Interrupts 8-1

Chapter 8

Interrupts

The TLSB supports both vectored and nonvectored interrupts.

• Vectored interrupts are the traditional I/O adapter interrupts, where

the processor dispatches the interrupt based on an IDENT (identifica-

tion) vector supplied by the adapter. The value of the IDENT vector is

loaded into each adapter at system initialization.

• Nonvectored interrupts are those interrupts that have been architec-

turally defined mechanisms for entering the relevant interrupt service

routine. These interrupts do not require IDENT vectors. Inter-

processor interrupts and system and error interrupts are examples of

nonvectored interrupts.

The TLSB interrupt mechanism allows multiple I/O controllers to generate

vectored interrupts without requiring new PALcode support for vectored

interrupt dispatch. The TLSB extends the interrupt mechanism to target

16 CPUs. The target of an interrupt is identified by the CPU virtual ID.

8.1 Vectored Interrupts

The TLSB supports up to five I/O interrupting nodes. Interrupts are re-

stricted to nodes 4 through 8. Thus, TLSB implements 5 interrupt level

registers, TLIOINTR4 –TLIOINTR8. To determine which of the five nodes

sent the interrupt request, the I/O devices write to the TLIOINTRn regis-

ter where n equals physical node ID. This informs the processor of the

pending interrupt request and because the write occurs to an indexed reg-

ister the CPU knows the physical node number of the requester.

To process an interrupt, software executes a read of the TLILIDn register

of the interrupting node. The data pattern written into TLIOINTRn speci-

fies one of four interrupt levels, which is used to select one of TLILID0 –

TLILID3.

The mapping of the bus interrupt levels to the processor IPLs is implemen-

tation specific. Each CPU must implement a 4-bit interrupt mask in a

node-specific register to enable/disable individual interrupt levels.

8.1.1 I/O Port Interrupt Rules

The I/O module posts interrupts to CPUs through writes to the TLIOIN-

TRn registers and obeys the following rules: