Specifications

2-8 TLSB Bus

2.2.3.1 Memory Bank Addressing Scheme

The TLSB supports one terabyte of physical memory. The memory ad-

dress space is accessed by a 40-bit byte address. The granularity of ac-

cesses on the TLSB is a 64-byte cache block. I/O adapters that need to ma-

nipulate data on boundaries less than 64 bytes require the commander

node to perform an atomic Read-Modify-Write transaction.

Physical memory on the TLSB is broken into banks. The commander de-

codes the 40-bit physical address into a memory bank number. TLSB sup-

ports a maximum of 16 memory banks in the system. Each commander

node contains eight memory mapping registers. Each mapping register

can decode two bank numbers.

A memory module can have multiple physical banks. Each bank is as-

signed a virtual bank number. The bank number is written in the TLVID

memory module these fields are named virtual bank numbers

MEM_BANKn, where n is in the range 0–15. This scheme, combined with

the address decoding scheme, permits flexible memory interleaving. When

an address is transmitted on the TLSB, the bank controllers on memory

nodes only need to perform a four-bit compare with the virtual ID to deter-

mine if the bank is being addressed. This decode is much quicker than a

full address decode. The address is propagated before the DRAM bank is

determined and RAS is asserted to the proper bank.

2.2.3.2 CSR Addressing Scheme

CSRs are accessed using two special command codes on the address bus.

Both local and remote CSRs can be accessed. Local CSRs exist on TLSB

nodes and can be directly accessed through the physical node ID. Remote

CSRs exist on I/O devices connected to I/O buses on I/O adapter nodes, and

must be accessed through the I/O node using its physical node ID. CSR

write commands can also be broadcast to all TLSB nodes in a single bus

transaction.

CSRs are accessed by the 37-bit address on the address bus. CSR accesses

to nonexistent nodes are not acknowledged. CSR accesses to a node that is

present in the system are always acknowledged on the address bus even if

the CSR does not exist. The node that acknowledges the address is respon-

sible for sequencing the data bus where 64 bytes of data are transferred. If

a read is performed to a valid node, but to a CSR that is not implemented,

the return data is Unpredictable.

CSR write commands addressing broadcast space are acknowledged by the

commander. If the commander acknowledges the command, it also se-

quences the data bus and transmits data. All receiving nodes optionally

implement the write command. If the CSR does not exist, then the broad-

cast write is ignored. Receiving nodes may take action based on the broad-

cast space address even if the command is not acknowledged, if no data is

needed (for example, a decrement counter operation). A read in broadcast

space is illegal, and the commander should not issue such a command. If a

broadcast space CSR read is detected on the bus, all nodes ignore the com-

mand.