Specifications

System Registers 7-141
Table 7-65 IBR Register Bit Definitions
Name Bit(s) Type Function
RSVD
<31:3> R/W, 0 Reserved. Read as zeros.
SCLK
<2> R/W, 0 Serial Clock. Used to implement the
FEPROM serial clock interface by software.
When this bit is written with a one, the
FEPROM serial clock input is forced to a logic
high. When this bit is cleared, the serial clock
input is forced to low logic level.
XMT_SDAT
<1> R/W, 1 Transmit Serial Data. Used by software to
assert the serial data line of the EEPROM to
either high or low logic level. This bit is used
with <SCLK> to transfer command, address,
and write data to the EEPROM.
RCV_SDAT
<0> R, 1 Receive Serial Data. Returns the status of
the EEPROM serial data line. This bit is used
by software to receive serial read data and
EEPROM responses.
NOTE: XMT_SDAT must be one to receive an
EEPROM response or serial read data.