Specifications

System Registers 7-129
Table 7-60 IDPNSE0–3 Register Bit Definitions
Name Bit(s) Type Function
HOSEn_RESET
<31> W, 0 HOSEn Reset. When this bit is written to a
one, the I/O port generates a reset to the associ-
ated hose as follows:
HOSEn_RESET in IDPNSE3 causes a reset
to be generated to HOSE 3
HOSEn_RESET in IDPNSE2 causes a reset
to be generated to HOSE 2
HOSEn_RESET in IDPNSE1 causes a reset
to be generated to HOSE 1
HOSEn_RESET in IDPNSE0 causes a reset
to be generated to HOSE 0
Reads to this bit position always return a zero.
RSVD
<30:29> R0 Reserved. Read as zeros.
IDR_CSR_BUS_PAR
_ERR
<28> W1C, 0 IDR CSR Bus Parity Error. When set, indi-
cates that the applicable IDRn data path gate
array detected a parity error on the CSR data
bus or the CSR address bus when receiving data
from the ICR or another IDRn gate array.
An IPL 17 interrupt is generated when this bit
sets if interrupts are enabled by INTR_NSES
(ICCNSE<31>.
IDR_INTR_ERR
<27> W1C, 0 IDR Internal Error. IDR_IE is a composite
error bit of all possible internal errors that can
be detected by the IDR data path gate array.
Each IDR gate array has its own IDR_IE bit.
The I/O port asserts IDR_IE under the following
conditions:
XB Buffer overflow/underflow
Up Turbo Vortex sequence error
TL CMD FIFO overflow
This is a fatal error that causes the I/O port to
drive TLSB_FAULT.