Specifications

System Registers 7-127

ICCWTR—I/O Control Chip Window Transaction Reg

Table 7-59 ICCWTR Register Bit Definitions

ddress

ccess

BB + 2100

The ICCWTR register indicates if a window transaction is in pro-

gress and the targeted hose of the transaction. This register is

physically located in the ICR gate array.

31 04

RSVD

BXB-0761-94

WIP<3:0>

Name Bit(s) Type Function

RSVD

<31:4> R0 Reserved. Read as zeros.

WIP<3:0>

<3:0> W1C, 0 Window in Progress. When set, these bits indi-

cate that the I/O port has at least one window com-

mand packet outstanding down the hose.

WIP<3:0> correspond to hoses 3 to 0, respectively.

Each time a window command packet is transmit-

ted down a hose, the associated WIP counter is in-

cremented. As long as the WIP counter is nonzero,

the corresponding WIP<3:0> bit remains set.

Writing one to a bit position in WIP<3:0> clears

the bit and its associated WIP counter. This is use-

ful if a window transaction fails to complete and

the WIP counter needs to be reset manually.