Specifications

TLSB Bus 2-5

2.2 Operation

This section offers an overview of the TLSB bus operations. Topics in-

clude:

• Physical node identification

• Virtual node identification

• Address bus concepts

• Address bus arbitration

• Address bus cycles

• Address bus commands

• Data bus concepts

• Data bus functions

• Miscellaneous bus signals

The reader is referred to the engineering specification for more detail on

the topics covered in this chapter.

2.2.1 Physical Node ID

The AlphaServer 8400 features nine nodes (corresponding to the nine

physical connectors) on the TLSB. Each CPU, memory, or I/O port module

receives signals TLSB_NID<2:0> to identify its node number. The

TLSB_NID<2:0> signals are selectively grounded and are pulled up on the

module. Node 0 and node 8 receive TLSB_NID<2:0> equal to zero. Since

an I/O port module is not permitted in node 0 and is the only module type

permitted in node 8, an I/O adapter that receives TLSB_NID<2:0> equal to

zero knows it is in node 8. Table 2-2 identifies the nodes on the TLSB.

The AlphaServer 8200 has nodes 4 to 8 only. Node 4 must be a CPU mod-

ule. Node 8 is dedicated to an I/O module.

Table 2-2 TLSB Physical Node Identification

TLSB_NID<2:0>

Node/Slot

Number Description

000

001

010

011

100

101

110

111

000

CPU or memory module

CPU, memory or I/O module

CPU, memory, or I/O module

I/O module