Specifications

7-110 System Registers

RMRR0-1—Memory Channel Range Registers

ddress

ccess

BB + 1E00 to 1EC0

R/W

The I/O port houses two incoming Memory Channel address range

but are generic across all four hoses. The I/O port compares the

addresses of all incoming DMA write packets to the contents of

these registers, regardless of the originating Up Hose.

One pair (RMRR0n) checks for matches of incoming DMA ad-

dresses targeted to an I/O port in TLSB node 8. The other pair

(RMRR1n) checks for matches of incoming DMA addresses tar-

geted to an I/O port in TLSB nodes 4, 5, 6, or 7.

After the I/O port has set the appropriate TLSB_ADR<4:3> bits, it

passes the DMA write to the TLSB as a normal memory write.

Incoming Memory Channel writes are never compared against the

RMRRs and thus are never reflected as outgoing writes.

31 30 0

BASE_ADR_A <39:20>

BXB-0782-93

VALID

28 2 7 4387

BASE_ADR_B <39:20>

RSVD

EXT_MASK

RSVD

INTLV_EN