Specifications

System Registers 7-109
7.6 I/O Port-Specific Registers
The I/O port responds to all addresses within its node space. If, however,
the I/O port receives a read to a nonimplemented CSR, the I/O port returns
Unpredictable data, with good ECC. Table 7-53 shows the mapping of the
I/O port-specific registers.
Table 7-53 I/O Port-Specifc Registers
Mnemonic Name Address
RMRR0A
RMRR1A
RMRR0B
RMRR1B
ICCMSR
ICCNSE
ICCDR
ICCMTR
ICCWTR
IDPNSE1
IDPDR1
IDPNSE2
IDPDR2
IDPNSE3
IDPDR3
IDPNSE0
IDPDR0
IPCPUMR
IDPVR
IDPMSR
IBR
DHR0A
DHR1A
DHR0B
DHR1B
Memory Channel Range Register 0A
Memory Channel Range Register 1A
Memory Channel Range Register 0B
Memory Channel Range Register 1B
I/O Control Chip Mode Select Register
I/O Control Chip Node-Specific Error Register
I/O Control Chip Diagnostic Register
I/O Control Chip Mailbox Transaction Register
I/O Control Chip Window Transaction Register
I/O Data Path Node-Specific Error Register 1
I/O Data Path Diagnostic Register 1
I/O Data Path Node-Specific Error Register 2
I/O Data Path Diagnostic Register 2
I/O Data Path Node-Specific Error Register 3
I/O Data-Path Diagnostic Register 3
I/O Data Path Node-Specific Error Register 0
I/O Data Path Diagnostic Register 0
IPCPU Mask Register
I/O Data Path Vector Register
I/O Data Path Mode Select Register
Information Base Repair Register
Down Hose Range Register 0A
Down Hose Range Register 1A
Down Hose Range Register 0B
Down Hose Range Register 1B
BB+1E00
BB+1E40
BB+1E80
BB+1EC0
BB+2000
BB+2040
BB+2080
BB+20C0
BB+2100
BB+2140
BB+2180
BB+2240
BB+2280
BB+2340
BB+2380
BB+2A40
BB+2A80
BB+2AC0
BB+2B40
BB+2B80
BB+2BC0
BB+3000
BB+3040
BB+3080
BB+30C0