Specifications

7-106 System Registers
DDR0:3—Data Diagnostic Registers
Table 7-52 DDRn Register Bit Definitions
A
ddress
A
ccess
BB + 0001 0140; 0001 04140; 0001 8140; 0001 C140
R/W
There are four DDR registers, one in each of the four MDI ASICs.
They are used by diagnostics and manufacturing to force error
conditions, to isolate failures, and to margin the DC to DC power
converters.
31 9 4 3 08 7 6
13
12
RSVD
BXB-0764-93
RSVD

CFLP: Check Bit to Flip
PAT: Self-Test Pattern Select
ICFR: Inhibit Clear on Free Run
CDER: Clear Self-Test Data Err Reg
LOE: Lock on Error
16 15 14
DFLP: Data Bit to Flip
EFLPC: Ena Flip ECC Check Bit
EFLPD: Ena Flip Data Bit
MARG: Margin
30
Name Bit(s) Type Function
MARG
<31> R/W, 0 Margin. When set, margins the module’s 5.0 V
and 3.35 V DC to DC converters over a +/− 5%
range.
Register Voltage Margin
DDR0
DDR1
DDR2
DDR3
5.0
5.0
3.5
3.5
+5%
−5%
+5%
−5%
RSVD
<30:16> R0 Reserved. Read as zero.