Specifications

System Registers 7-97
MER—Memory Error Register
Table 7-47 MER Register Bit Definitions
A
ddress
A
ccess
BB + 0000 1940
R/W
The MER register provides the DRAM string that failed when an
ECC error is detected during a memory read transaction. This in
-
formation in conjunction with the error syndrome registers can be
used to isolate correctable ECC errors down to a failing DRAM
component. This information is logged by the OS error logging
software and written to the serial EEPROM.
31 43 02
FSTRRSVD
BXB-0751-94
Name Bit(s) Type Function
RSVD
<31:3> R0 Reserved. Read as zero.
FSTR
<2:0> R, 0 Failing String. This field indicates which of
the eight strings was being accessed during a
TLSB memory read or memory write when an
uncorrectable or correctable ECC error was de-
tected and, together with the four syndrome reg-
isters and the failing address registers, isolates
single-bit errors to a failing DRAM component.
This field is locked on the occurrence of a
correctable or uncorrectable error detected in
any of the four MDI ASICs.