Specifications

7-96 System Registers
Table 7-46 STER Register Bit Definitions
Name Bit(s) Type Function
RSVD
<31:8> R0 Reserved. Read as zero.
STE3
<7> W1C, 0 Self-Test Error in MDI3. Set during POEM mode when
MDI3 detects a data mismatch error. The setting of this
bit locks bit <6> (STE2), bit <5> (STE1), bit <4> (STE0),
and bits <2:0> (FSTR) of the failing string field
1
.
STE2
<6> W1C, 0 Self-Test Error in MDI2. Set during POEM mode when
MDI2 detects a data mismatch error. The setting of this
bit locks bit <7> (STE3), bit <5> (STE1), bit <4> (STE0),
and bits <2:0> (FSTR) of the failing string field
1
.
STE1
<5> W1C, 0 Self-Test Error in MDI1. Set during POEM mode when
MDI1 detects a data mismatch error. The setting of this
bit locks bit <7> (STE3), bit <6> (STE2), bit <4> (STE0),
and bits <2:0> (FSTR) of the failing string field
1
.
STE0
<4> W1C, 0 Self-Test Error in MDI0. Set during POEM mode when
MDI0 detects a data mismatch error. The setting of this
bit locks bit <7> (STE3), bit <6> (STE2), bit <5> (STE1),
and bits <2:0> (FSTR) of the failing string field
1
.
RSVD
<3> R0 Reserved. Read as zero.
FSTR
<2:0> R Failing String. When read together with the <STEx>
bits, this field indicates the failing DRAM string when a
data mismatch error is detected by self-test. This field is
Undefined if none of the <STEx> bits are set.
1
Any one STER bit being set will prevent the other STER bits from being set on a subsequent data mismatch during
self-test. More than one STER bit may be set if multiple MDI ASICs detect a data mismatch during the same cycle. A
data mismatch error is defined as any failure that is detected within a 64-byte block that is considered to be a bus
transaction.