Specifications

System Registers 7-95
STER—Self-Test Error Register
A
ddress
A
ccess
BB + 0000 1900
R/W
The STER register contains address information pertaining to dat
a
mismatch failures while self-test executes in POEM (pause on er-
ror) mode. The contents of this register when read after an error
has been detected in POEM mode can be used to isolate the failing
DRAM string and to indicate which of the four MDIs the error was
detected in. This information in conjunction with the four ST-
DERA:E registers located in the MDI ASICs can be used to isolate
down to a failing DRAM bit or bits. This register is cleared when
MDRA<POEMC> is asserted.
BXB-0750-93
RSVD
31 43 08765 2
FSTR
STE0
STE1
STE2
STE3
RSVD