Specifications

7-94 System Registers
Table 7-45 STAIR Register Bit Correspondence of Memory Address Segments
Each module executes self-test as if it were the only memory module in the
system (no interleave with other modules).
Assuming a given processor takes approximately 600 nanoseconds to scan
each 64-byte block of memory for uncorrectable ECC errors, a 64-Mbyte
failing address segment (1 meg 64-byte blocks, with failures in each block)
can be scanned from first to last block in about 600 milliseconds.
Bit Set Failing Address Range Bit Set Failing Address Range
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000 0000 – 03FF FFFF
0400 0000 – 07FF FFFF
0800 0000 – 0BFF FFFF
0C00 0000 – 0FFF FFFF
1000 0000 – 13FF FFFF
1400 0000 – 17FF FFFF
1800 0000 – 1BFF FFFF
1C00 0000 – 1FFF FFFF
2000 0000 – 23FF FFFF
2400 0000 – 27FF FFFF
2800 0000 – 2BFF FFFF
2C00 0000 – 2FFF FFFF
3000 0000 – 33FF FFFF
3400 0000 – 37FF FFFF
3800 0000 – 3BFF FFFF
3C00 0000 – 3FFF FFFF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
4000 0000 – 43FF FFFF
4400 0000 – 47FF FFFF
4800 0000 – 4BFF FFFF
4C00 0000 – 4FFF FFFF
5000 0000 – 53FF FFFF
5400 0000 – 57FF FFFF
5800 0000 – 5BFF FFFF
5C00 0000 – 5FFF FFFF
6000 0000 – 63FF FFFF
6400 0000 – 67FF FFFF
6800 0000 – 6BFF FFFF
6C00 0000 – 6FFF FFFF
7000 0000 – 73FF FFFF
7400 0000 – 77FF FFFF
7800 0000 – 7BFF FFFF
7C00 0000 – 7FFF FFFF