Specifications

7-92 System Registers
Table 7-43 MCR Register Bit Definitions (Continued)
Name Bit(s) Type Function
DTR
<5:4> R/W, 0 DRAM Timing Rate. This field is used to mod-
ify the DRAM timing and refresh rate. At reset,
DRAM timing defaults to supporting a 10 ns bus
cycle time, while the refresh rate defaults to sup-
porting a 30 ns bus. <DTR> is normally written
by console through a TLSB broadcast write com-
mand. This ensures that all memories will re-
main syncronized as to when they refresh the
DRAMs. The <DTR> field should not be changed
from the value set by console when other bits in
this field are modified.
DTR
Bus Speed
Range
Refresh Counter
Value
00 (Def)
01
10
11
10.0 - 11.2
Reserved
12.5 - 13.7
13.8 - 15.0
1360
None
1088
1008
STRN
<3:2> R, X
1
Strings Installed. This field supplies informa-
tion about the number of strings installed on a
module.
STRN Strings
00
01
10
11
1
2
4
8
RSVD
<1> R0 Reserved. Read as zero.
DTYP
<0> R, X
1
DRAM Type. This field supplies information
about what size DRAM technology is being used;
this together with the number of strings in-
stalled determines module capacity.
DTYP DRAM Type
0
1
4 Mbit
16 Mbit
1
Value loaded into register at system initialization/reset through manufacturing installed jumpers on the module.