Specifications

iii
Contents
Preface ............................................................................................................................................ xv
Chapter 1 Overview
1.1 Configuration ................................................................................................................ 1-1
1.2 Bus Architecture ........................................................................................................... 1-2
1.3 CPU Module .................................................................................................................. 1-3
1.3.1 DECchip 21164 ...................................................................................................... 1-3
1.3.2 Backup Cache ......................................................................................................... 1-4
1.3.3 TLSB Interface ....................................................................................................... 1-4
1.3.4 Console Support Hardware....................................................................................1-4
1.4 Memory Module ............................................................................................................ 1-4
1.5 I/O Architecture ............................................................................................................ 1-5
1.6 Software......................................................................................................................... 1-6
1.6.1 Console .................................................................................................................... 1-6
1.6.2 OpenVMS Alpha ..................................................................................................... 1-7
1.6.3 Digital UNIX........................................................................................................... 1-7
1.6.4 Diagnostics.............................................................................................................. 1-7
1.6.4.1 ROM-Based Diagnostics .................................................................................. 1-7
1.6.4.2 Loadable Diagnostic Execution Environment ...............................................1-8
1.6.4.3 Online Exercisers ............................................................................................. 1-8
Chapter 2 TLSB Bus
2.1 Overview........................................................................................................................ 2-1
2.1.1 Transactions ........................................................................................................... 2-2
2.1.2 Arbitration .............................................................................................................. 2-2
2.1.3 Cache Coherency Protocol......................................................................................2-2
2.1.4 Error Handling ....................................................................................................... 2-2
2.1.5 TLSB Signal List .................................................................................................... 2-3
2.2 Operation....................................................................................................................... 2-5
2.2.1 Physical Node ID .................................................................................................... 2-5
2.2.2 Virtual Node Identification .................................................................................... 2-6
2.2.3 Address Bus Concepts ............................................................................................2-6
2.2.3.1 Memory Bank Addressing Scheme ................................................................. 2-8
2.2.3.2 CSR Addressing Scheme.................................................................................. 2-8
2.2.3.3 Memory Bank Address Decoding .................................................................... 2-9
2.2.3.4 Bank Available Status ................................................................................... 2-11
2.2.3.5 Address Bus Sequencing................................................................................ 2-11
2.2.4 Address Bus Arbitration ...................................................................................... 2-12
2.2.4.1 Initiating Transactions .................................................................................. 2-12
2.2.4.2 Distributed Arbitration.................................................................................. 2-12