Specifications

System Registers 7-81
GBUS$MISCW
Table 7-38 GBUS$MISCW Register Bit Definitions
A
ddress
A
ccess
FF C500 0000
W
The GBUS$MISCW register is used to gather write bits that contro
l
various functions.
43 0765 12
BXB-0515-93
CACSIZ: B-Cache Size
DRIVE_BAD
TLSB_SECURE
CONWIN1R
CONWIN0R
RSVD
TLSB_RUN
Name Bit(s) Type Function
CONWIN1W
CONWIN0W
DRIVE_CONWIN
DRIVE_RUN
FPROM_WE
DRIVE_BAD
RSVD
<7>
<6>
<5>
<4>
<3>
<2>
<1:0>
W, 0
W, 0
W, 0
W, 0
W, 0
W, 0
W, 0
Console Winner CPU1 Write. This bit is set to
indicate that CPU1 has won console arbitration.
Console Winner CPU0 Write. This bit is set to
indicate that CPU0 has won console arbitration.
Drive Console Winner. Written when this mod-
ule has won arbitration for console.
Drive Run. Written when this module is running
an operating system.
FEPROM Write Enable. When set, writes to the
FEPROM are enabled. FEPROM update and re-
covery programs must set this bit prior to writing
FEPROM and clear it after writing is complete.
Drive TLSB Bad. If set, drives the TLSB_BAD
line. The CPU drives this line if self-test has not
yet passed, or if it determines that another module
that the CPU is testing (for example, I/O port) or
monitoring (XMI or Futurebus+ adapters) has
failed.
Reserved. Must be zero.