Specifications

TLSB Bus 2-1
Chapter 2
TLSB Bus
This chapter provides a brief overview of the TLSB bus. For more detailed
discussions and timing diagrams for the various bus cycles, refer to the
TurboLaser System Bus Specification.
2.1 Overview
The TLSB bus is a limited length, nonpended, synchronous bus with a
separate address and data path. Ownership of the address bus is deter-
mined using a distributed arbitration protocol. The data bus does not re-
quire an arbitration scheme. The data bus transfers data in the sequence
order in which command/addresses occur. The combination of separate ad-
dress and data paths with an aggressive arbitration scheme permits a low
latency protocol to be implemented.
Because the address and data buses are separate, there is maximum over-
lap between command issues and data return. The TLSB also assumes
that the CPU nodes run the module internal clock synchronous to the bus
clock, eliminating synchronizers in the bus interface and their associated
latency penalties. The TLSB provides control signals to permit nodes to
control address and data flow and minimize buffering.
The TLSB operates over a range of 10 to 30 ns clock cycles. This corre-
sponds to a maximum bandwidth of 2.1 Gbytes/sec and a projected mini-
mum latency of 170 ns with a 10 ns clock cycle. Memory latency is reduced
by improving the DRAM access time. Because the address bus and data
bus are separate entities, the slot for passing data on the data bus is vari-
able and directly affected by the DRAM access time. Therefore, any de-
crease in DRAM access time is reflected in a decrease in memory latency.
The AlphaServer 8400 has nine physical nodes on the TLSB centerplane,
numbered 0–8. CPU and memory modules are restricted to nodes 0–7. I/O
ports are restricted to nodes 4–8. These five nodes are on the back side of
the centerplane. AlphaServer 8200 supports the five backplane nodes
only. I/O modules are restricted to nodes 6, 7, and 8. Node 8 in both mod-
els is dedicated to the I/O module and has the special property of both high
and low priority arbitration request lines that are used to guarantee that
memory latency is no worse than 1.7 µs. An I/O port in any other node
uses the standard arbitration scheme, and no maximum latency is speci-
fied.